Hello,
I am getting started with the whole QSys tool and I am learning by following tutorials and videos. In particular, I want to be able to perform simulations of what I am constructing in ModelSIM. I started off watching this video: http://www.altera.com/education/demonstrations/qsys/simulation/simulation-online-demo.html . I did exactly what is done in the video. I added an On-Chip RAM and exported the clk, the s1 and the reset signals. https://www.alteraforum.com/forum/attachment.php?attachmentid=7830 https://www.alteraforum.com/forum/attachment.php?attachmentid=7831 However, when I want to generate the testbench and BFMs it gives me an error I don't really understand. It tells me that there are two reset ports. However, I only see one. What is going on? https://www.alteraforum.com/forum/attachment.php?attachmentid=7832 https://www.alteraforum.com/forum/attachment.php?attachmentid=7833 Error: TB_Gen: More than one reset ports found Error: get_instance_interface_port_property ram_inst ram_reset1 ROLE: null Error: Error: TB_Gen: More than one reset ports found get_instance_interface_port_property ram_inst ram_reset1 ROLE: null Error: There were errors creating the testbench system. What is the cause of the error and how do I fix this? Thanks.链接已复制
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Hi Alex, which Quartus 2 version are you using?
I've always used this tutorial with version 13.0 and 13.0 sp1 without any problem, everything worked correctly. Now I have installed version 13.1 and it does not work anymore. It seems that it's another Altera bug. Furthermore I kept the older version (13.0 installed) in the same PC, and now it doesn't work it either....this seems more strange LucaI found that the problem is due to the new On-Chip RAM, that has 2 reset inputs: if you want to manage thus problem you have to put a clock source and connect reset_out and clk_out of the clock source to the RAM and then export the clock_source clock and reset inputs
