Simulating Cyclone V altera_hps with ModelSim

[Altera_Forum]

Quartus 18.0 Standard, ModelSim Intel FPGA Starter Edition 10.5b. 

 Trying to simulate a design that contains a Platform Designer generated instance of altera_hps (for access to HPS-side DDR3 RAM via the FPGA to HPS bridge).   First I tried to follow the instructions from the Qsys/Platform Designer tutorial. I got Platform Designer to generate the simulation script, then fired up ModelSim and loaded it. It complained about MvcHome not being set, then gave me a few hundred errors of the kind # ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_find' in DPI C/C++ source files.# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_valid' in DPI C/C++ source files.# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_advance' in DPI C/C++ source files.# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_release' in DPI C/C++ source files.# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh   finished off by # ** Fatal: (vsim-160) ./soc_system/simulation/submodules/mgc_common_axi.sv(3173): Null foreign function pointer encountered when calling 'axi_initialise_SystemVerilog'# Time: 0 ps Iteration: 0 Process: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces/f2h_axi_slave_inst/axi/#INITIAL#3193 File: ./soc_system/simulation/submodules/mgc_common_axi.sv# FATAL ERROR while loading design   As far as I could establish after a *lot* of digging (and correct me if I'm wrong), this requires a bus functional model (BFM) for the AXI bus, and it is not included in ModelSim Starter Edition and requires a separate paid license.  Abandoned this approach and tried to load simulation out of Quartus. Oddly, this time it tries to load sources from soc_system/synthesis/submodules instead of soc_system/simulation/submodules, which is why errors are different. After resolving most load failures, I end up with:   Loading soc_system.soc_system_hps_0# Loading soc_system.soc_system_hps_0_fpga_interfaces# ** Error: (vsim-3033) C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv(151): Instantiation of 'cyclonev_hps_interface_clocks_resets' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces File: C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv# Searched libraries:# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/altera_mf# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_mf# C:/Development/fpga/DE10_DDR3/simulation/modelsim/soc_system# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/cyclonev# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev_hssi# C:/Development/fpga/DE10_DDR3/simulation/modelsim/rtl_work# ** Error: (vsim-3033) C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv(170): Instantiation of 'cyclonev_hps_interface_dbg_apb' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces File: C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv# Searched libraries:# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/altera_mf# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_mf# C:/Development/fpga/DE10_DDR3/simulation/modelsim/soc_system# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/cyclonev# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev_hssi# C:/Development/fpga/DE10_DDR3/simulation/modelsim/rtl_work ... and a bunch of others (e.g. cyclonev_hps_peripheral_emac and cyclonev_hps_peripheral_usb), 17 total.  None of those seem to be implemented in software or known to ModelSim.  Do I understand correctly that Cyclone V designs using altera_hps IP simply can't be simulated without paying more money for another license?  Some googling turned up the part number for the license that seems to be needed - IPS-AXIBFM ( http://www.alteraforum.com/forum/showthread.php?t=42038 ) - and it is $495 on Mouser. Seriously? I paid $130 for the board ...

[Altera_Forum]

FWIW, it does load if I don't use AXI bridges and stick to f2h_sdram0_data declared as an Avalon-MM slave.  

 It does not really work though. The read request goes out, "waitrequest" is asserted, and the response never arrives. There is a ton of debug messages about precharging and refreshing banks in the console, so, at least it tries to simulate the RAM.

[Altera_Forum]

--- Quote Start ---  Quartus 18.0 Standard, ModelSim Intel FPGA Starter Edition 10.5b.  Trying to simulate a design that contains a Platform Designer generated instance of altera_hps (for access to HPS-side DDR3 RAM via the FPGA to HPS bridge).   First I tried to follow the instructions from the Qsys/Platform Designer tutorial. I got Platform Designer to generate the simulation script, then fired up ModelSim and loaded it. It complained about MvcHome not being set, then gave me a few hundred errors of the kind # ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_find' in DPI C/C++ source files.# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_valid' in DPI C/C++ source files.# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_advance' in DPI C/C++ source files.# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh# ** Warning: (vsim-3770) Failed to find user specified function 'questa_mvc_sv_release' in DPI C/C++ source files.# Time: 0 ps Iteration: 0 Region: /QUESTA_MVC File: ./soc_system/simulation/submodules/questa_mvc_svapi.svh   finished off by # ** Fatal: (vsim-160) ./soc_system/simulation/submodules/mgc_common_axi.sv(3173): Null foreign function pointer encountered when calling 'axi_initialise_SystemVerilog'# Time: 0 ps Iteration: 0 Process: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces/f2h_axi_slave_inst/axi/#INITIAL#3193 File: ./soc_system/simulation/submodules/mgc_common_axi.sv# FATAL ERROR while loading design   As far as I could establish after a *lot* of digging (and correct me if I'm wrong), this requires a bus functional model (BFM) for the AXI bus, and it is not included in ModelSim Starter Edition and requires a separate paid license.  Abandoned this approach and tried to load simulation out of Quartus. Oddly, this time it tries to load sources from soc_system/synthesis/submodules instead of soc_system/simulation/submodules, which is why errors are different. After resolving most load failures, I end up with:   Loading soc_system.soc_system_hps_0# Loading soc_system.soc_system_hps_0_fpga_interfaces# ** Error: (vsim-3033) C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv(151): Instantiation of 'cyclonev_hps_interface_clocks_resets' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces File: C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv# Searched libraries:# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/altera_mf# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_mf# C:/Development/fpga/DE10_DDR3/simulation/modelsim/soc_system# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/cyclonev# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev_hssi# C:/Development/fpga/DE10_DDR3/simulation/modelsim/rtl_work# ** Error: (vsim-3033) C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv(170): Instantiation of 'cyclonev_hps_interface_dbg_apb' failed. The design unit was not found.# Time: 0 ps Iteration: 0 Instance: /DE10_NANO_SoC_GHRD/u0/hps_0/fpga_interfaces File: C:/Development/fpga/DE10_DDR3/soc_system/synthesis/submodules/soc_system_hps_0_fpga_interfaces.sv# Searched libraries:# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/altera_mf# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_mf# C:/Development/fpga/DE10_DDR3/simulation/modelsim/soc_system# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/cyclonev# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev# C:/intelFPGA/18.0/modelsim_ase/altera/vhdl/altera_lnsim# C:/intelFPGA/18.0/modelsim_ase/altera/verilog/cyclonev_hssi# C:/Development/fpga/DE10_DDR3/simulation/modelsim/rtl_work ... and a bunch of others (e.g. cyclonev_hps_peripheral_emac and cyclonev_hps_peripheral_usb), 17 total.  None of those seem to be implemented in software or known to ModelSim.  Do I understand correctly that Cyclone V designs using altera_hps IP simply can't be simulated without paying more money for another license?  Some googling turned up the part number for the license that seems to be needed - IPS-AXIBFM ( http://www.alteraforum.com/forum/showthread.php?t=42038 ) - and it is $495 on Mouser. Seriously? I paid $130 for the board ...  --- Quote End ---    I am getting the same errors you mentioned at the top. No one from Altera/Intel has offered suggestions?