I recently started using Intel Quartus Prime Lite edition for simulating Verilog codes.
I came across the topic of gate delays in a book..
for eg. In a verilog code if I write a line of code as such :
module simple_circuit(A, B, C, D, E);
input A, B, C;
output D, E;
and #30 G1 (w1, A, B);
not #10 G2 (E,C);
or #20 G3 (D, w1, E);
how do I view the simulation of gate delays.?
Look into example from below link.
If you are using modelsim/VWF
Launch gate level simulation from tools/VWF->Run simulation Tools->Gate level/timing simulation. Before that you need to setup path go to tools->options->EDA Tools option->modelsim altera ->give the modelsim path example "C:\intelFPGA\17.0\modelsim_ase\win32aloem".
You can find more useful information from previous threads kindly check below threads.