Simulation Runtime Error

[lrobe12]

Hi there , I'm extremely new to Quartus hence this probably rookie problem.

Basically upon trying to simulate my basic circuit with ModelSim I have an error which is attached below.I have checked the vhdl code and all seems fine ( line 12 of the vhdl would be line 39 as all above are comments).

Any help would be great.

[SyafieqS]

Hi Lauren,

Assuming you have done the compilation

1. Go to your project, select your hdl and testbench, then click simulate on the window option.
2. A start simulation window will pop out
3. In the library (for you gate_work i guess) select your testbench and hdl file, right click and click simulate.
4. A window simulation will pop up. select your desired signal in the object window, select them and add wave (depend on what signal you want to simulate)
5. Click run on the window option to run the simulation.

Thanks,

Regards