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Hello, everyone,
I get this error when I try to simulate the behavior of a state machine:
Determining the location of the ModelSim executable...
Using: C:\intelFPGA_lite\20.1\modelsim_ase\win32aloem
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off vendingmachine -c vendingmachine --vector_source="C:/VHDL code/Vending machine/Waveform.vwf" --testbench_file="C:/VHDL code/Vending machine/simulation/qsim/Waveform.vwf.vht"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Feb 13 14:23:35 2021
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off vendingmachine -c vendingmachine --vector_source="C:/VHDL code/Vending machine/Waveform.vwf" --testbench_file="C:/VHDL code/Vending machine/simulation/qsim/Waveform.vwf.vht"
Info (119006): Selected device 5CGXFC7C7F23C8 for design "vendingmachine"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
**** Generating the functional simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/VHDL code/Vending machine/simulation/qsim/" vendingmachine -c vendingmachine
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
Info: Copyright (C) 2020 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Sat Feb 13 14:23:36 2021
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/VHDL code/Vending machine/simulation/qsim/" vendingmachine -c vendingmachine
Info (119006): Selected device 5CGXFC7C7F23C8 for design "vendingmachine"
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file vendingmachine.vho in folder "C:/VHDL code/Vending machine/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4721 megabytes
Info: Processing ended: Sat Feb 13 14:23:37 2021
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01
Completed successfully.
**** Generating the ModelSim .do script ****
C:/VHDL code/Vending machine/simulation/qsim/vendingmachine.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vsim -c -do vendingmachine.do
Reading pref.tcl
# 2020.1
# do vendingmachine.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 14:23:38 on Feb 13,2021
# vcom -work work vendingmachine.vho
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package dffeas_pack
# -- Loading package altera_primitives_components
# -- Loading package altera_lnsim_components
# -- Loading package cyclonev_atom_pack
# -- Loading package cyclonev_components
# -- Compiling entity vendingmachine
# -- Compiling architecture structure of vendingmachine
# End time: 14:23:38 on Feb 13,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 14:23:38 on Feb 13,2021
# vcom -work work Waveform.vwf.vht
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity vendingmachine_vhd_vec_tst
# -- Compiling architecture vendingmachine_arch of vendingmachine_vhd_vec_tst
# End time: 14:23:39 on Feb 13,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Error loading design
Error loading design
Error: can't read "FileWatch(fileName)": no such element in array
Error.
I'm teaching VHDL and I need this to work for my courses and lab session. I used this tool regularely with Quartus18 and I never had this problem.
Please help me.
Hervé
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I able to run the simulation though. I run full compilation, open waveform.vwf file.
In the simulation > simulation setting, remove the -novopt in the modelsim script.
Run functional simulation and the simulation result will be shown.
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I able to run the simulation though. I run full compilation, open waveform.vwf file.
In the simulation > simulation setting, remove the -novopt in the modelsim script.
Run functional simulation and the simulation result will be shown.
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It works !!
Thanks for your help !
Hervé
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