Simulation gets rid of nodes?

Altera_Forum · ‎03-21-2008

I'm trying to do some debugging by seeing whats in all of my signals. In my .vwf file I go to node finder and I set my filter to Design Entry (all names) and I can see certain signals such as instructions and stuff which are labeled as type Combination Group. I add this to my waveform under type COMB and it appears in my waveform. Then when I run my functional simulation, the report doesn't show those signals, just the non combinational group ones. How can I get these to show up?

Altera_Forum · ‎03-21-2008

The normal reason is, that these signals are presynthesis signals and don't exist after compilation. A combinational signal generally can't be preserved in compilation, if it isn't a real signal, could be an output signal or also an input to a register.

Altera_Forum · ‎03-21-2008

So there's no way to see the values of these signals? I can't just dump them into outputs b/c that happens later so I won't ever get the timing right that way.

Altera_Forum · ‎03-21-2008

i would like to join this question subject and add some example of my own :

hi.

i have encountered a strange bug related to the Quatrus II web edition

i am using a simple module which sends data to another simple model - on a wire called "to_bcd3"

for the same reason mentioned before

when i am trying to debug the module ( Bug number 1) by adding the "to_bcd3" wire the simulation results plot

i am receiving a warning "this line was not found" though i added the line using the "Node finder"

so in order to view this line on the simulation plot - i changed the outer module :

this is the file before:

----------------------------------

module Bin_to_bcd_top( iBin, oBCD);

wire [9:0] to_bcd3;

This are the the only changes i have made

-------------------------------------------------------------

changed : module Bin_to_bcd_top( iBin, oBCD, to_Bcd3);

added : output [15:0] to_Bcd3;

what drives me nuts is this - not only that now i could debug the line's data

(which is good) but the bug had mysteriously disappeared !!!

and the module works just fine now....

of course if i'll remove the line from being an output - the inner module will again

stop receiving the data.

appreciate any help