Simulation/synthesis mismatch

[Altera_Forum]

My design uses lvds transmitters and receivers. When I use a serialization factor >2 it works fine. I need to use a serialization factor of 2, which converts the lvds blocks to ddio primitives. The pinouts seem to get messed up during this conversion. Simulation with Modelsim works fine, but it doesn't do the conversion to ddio. 

 Is there a way to generate a simulation netlist for a single component? I want to use a functional netlist from synthesis in Modelsim for that one component. The only thing I've found is the "nonfunctional" simulation netlist for power estimation.  Thanks, Myles

[Altera_Forum]

You could create a Quartus project with that one component and set all the ports to virtual pins. Set up Simulation EDA settings to generate a vho file. Then use the vho in your simulation.

[Altera_Forum]

Thanks for the idea. I'll try it out. I was going through the 34MB (1 M lines) .vo for the whole project, and I was having trouble telling which signal inversions to keep. I was afraid if I just had one component in the project it would get optimized away or use the wrong kind of pin.