Simulation using ModelSim

Altera_Forum · ‎05-23-2012

Hi..

i am simulating a project using modelsim i am facing some problems

1. i have written a test bench for my simulation and assigning some data at input port witch is 8bit wide and suppose to receive packet of data which is 53bytes long

2. when i am trying to input a data it is accepting only one byte at a time

3.how to input a data which is a packet of 53bytes to my input port.

please help me

thank you

Altera_Forum · ‎05-23-2012

well post some code and your testbench and we'll see.

With a testbench you can do a load of stuff you cannot do in synthesisable VHDL, so its very easy to control data flow.

Altera_Forum · ‎06-22-2012

Dear sir here is the code for test bench....

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_arith.ALL;

USE ieee.std_logic_unsigned.ALL;

LIBRARY lpm;

USE lpm.lpm_components.ALL;

LIBRARY work;--(i added this library)

USE work.voq_input_package.ALL;

entity voq_switch_tb is

end voq_switch_tb;

architecture tb of voq_switch_tb is

component voq_switch is

PORT (

fp1 : IN STD_LOGIC; --input frame pulse lines

fp2 : IN STD_LOGIC;

fp3 : IN STD_LOGIC;

fp4 : IN STD_LOGIC;

data_in1 : IN BYTE; --input data byte lines

data_in2 : IN BYTE;

data_in3 : IN BYTE;

data_in4 : IN BYTE;

global_reset : IN STD_LOGIC; --Resets all the counters,registers and the buffer

reset : IN STD_LOGIC; --Resets everything but the buffer

clock : IN STD_LOGIC;

fp_out_port1 : OUT STD_LOGIC; --output frame pulse lines-

fp_out_port2 : OUT STD_LOGIC;

fp_out_port3 : OUT STD_LOGIC;

fp_out_port4 : OUT STD_LOGIC;

data_out_port1 : OUT BYTE; --output data_lines

data_out_port2 : OUT BYTE;

data_out_port3 : OUT BYTE;

data_out_port4 : OUT BYTE;

data_valid1 : OUT STD_LOGIC; --output data_valid lines

data_valid2 : OUT STD_LOGIC;

data_valid3 : OUT STD_LOGIC;

data_valid4 : OUT STD_LOGIC;

--Source port number

incoming_port_to_output1 : OUT STD_LOGIC_VECTOR (2

DOWNTO 0);

incoming_port_to_output2 : OUT STD_LOGIC_VECTOR (2

DOWNTO 0);

incoming_port_to_output3 : OUT STD_LOGIC_VECTOR (2

DOWNTO 0);

incoming_port_to_output4 : OUT STD_LOGIC_VECTOR (2

DOWNTO 0);

--Priority vector output for simulation purpose

P : OUT STD_LOGIC_VECTOR (7 DOWNTO 1);

--request to scheduler and grant coming from scheduler for simulation

request : OUT STD_LOGIC_VECTOR(16 DOWNTO 1);

grant : OUT STD_LOGIC_VECTOR(16 DOWNTO 1)

);

end component;

signal fp1: STD_LOGIC:='0';

signal fp2: STD_LOGIC:='0';

signal fp3: STD_LOGIC:='0';

signal fp4: STD_LOGIC:='0';

signal data_in1,data_in2,data_in3,data_in4: BYTE:="00000000";

signal global_reset: STD_LOGIC:='0';

signal reset : STD_LOGIC:='0'; --Resets everything but the buffer

signal clock : STD_LOGIC:='1';

signal fp_out_port1 : STD_LOGIC:='0'; --output frame pulse lines-

signal fp_out_port2 : STD_LOGIC:='0';

signal fp_out_port3 : STD_LOGIC:='0';

signal fp_out_port4 : STD_LOGIC:='0';

signal data_out_port1 : BYTE:="00000000"; --output data_lines

signal data_out_port2 : BYTE:="00000000";

signal data_out_port3 : BYTE:="00000000";

signal data_out_port4 : BYTE:="00000000";

signal data_valid1 : STD_LOGIC:='0'; --output data_valid lines

signal data_valid2 : STD_LOGIC:='0';

signal data_valid3 : STD_LOGIC:='0';

signal data_valid4 : STD_LOGIC:='0';

--Source port number

signal incoming_port_to_output1 : STD_LOGIC_VECTOR (2 DOWNTO 0);

signal incoming_port_to_output2 : STD_LOGIC_VECTOR (2 DOWNTO 0);

signal incoming_port_to_output3 : STD_LOGIC_VECTOR (2 DOWNTO 0);

signal incoming_port_to_output4 : STD_LOGIC_VECTOR (2 DOWNTO 0);

--Priority vector output for simulation purpose

signal P : STD_LOGIC_VECTOR (7 DOWNTO 1);

--request to scheduler and grant coming from scheduler for simulation

signal request : STD_LOGIC_VECTOR(16 DOWNTO 1);

signal grant : STD_LOGIC_VECTOR(16 DOWNTO 1);

constant num_cycles : integer := 320;

begin

U_voq_switch:voq_switch port map(

fp1,fp2,fp3,fp4,

data_in1,data_in2,data_in3,data_in4,

global_reset,

reset,

clock,

fp_out_port1,fp_out_port2,fp_out_port3,fp_out_port4,

data_out_port1,data_out_port2,data_out_port3,data_out_port4,

data_valid1,data_valid2,data_valid3,data_valid4,

incoming_port_to_output1,incoming_port_to_output2,incoming_port_to_output3, incoming_port_to_output4,

P,

request,

grant

);

-- architecture declarative part

-- constant num_cycles : integer := 320;

--signal clock : std_ulogic := '1';

-- architecture statement part

process

begin

--for i in 1 to num_cycles loop

for i in 1 to 100 loop

clock <= not clock;

wait for 10 ns;

clock <= not clock;

wait for 10 ns;

-- clock period = 10 ns

end loop;

wait; -- simulation stops here

end process;

-- concurrent process to offer clock signal

--process

--begin

--clock <= '0';

-- wait for 5 ns;

-- clock <= '1';

--wait for 5 ns;

-- end process;

process

variable err_cnt:integer:=0;

begin

-- case 1

fp1 <= '1';

wait for 20 ns;

fp1<='0';

wait for 10 ns;

data_in1 <= "00000110";

wait for 20 ns;

data_in1 <= "00000111";

wait for 20 ns;

data_in1 <= "00001000";

wait for 20 ns;

data_in1 <= "00001001";

wait for 20 ns;

data_in1 <= "00001010";

wait for 20 ns;

data_in1 <= "00111010";

-- assert (data_out_port1="11111111") report "Sum Error!" severity error;

--assert (carry='0') report "Carry Error!" severity error;

-- if (data_out_port1/="01010101" ) then

-- err_cnt:=err_cnt+1;

-- end if;

-- summary of testbench

if (err_cnt=0) then

assert false

report "Testbench of Adder completed successfully!"

severity note;

else

assert true

report "Something wrong, try again"

severity error;

end if;

wait;

end process;

end TB;

--------------------------------------------------------------------

configuration CFG_TB of voq_switch_tb is

for TB

end for;

end CFG_TB;

--------------------------------------------------------------------

Altera_Forum · ‎06-22-2012

you need to add more data to the second process. I also suggest making it sensitive to clock rather than waiting for time periods between inputs.