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Hi, I had a problem studying verilog alone
The basic code was compiled well as shown in the picture below.
Next, I simulated it, but all the code was completed successfully, but at the end, an error occurred without any explanation.
Below is the full text of the simulation flow progress.
-------------------------------------------------------------------------
Determining the location of the ModelSim executable...
Using: c:/intelfpga_lite/22.1std/questa_fse/win64/
To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used.
**** Generating the ModelSim Testbench ****
quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off AlteraProject -c AlteraProject --vector_source="C:/VerilogHDL/test/Waveform.vwf" --testbench_file="C:/VerilogHDL/test/simulation/qsim/Waveform.vwf.vt"
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Wed Jul 26 12:24:40 2023
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off AlteraProject -c AlteraProject --vector_source=C:/VerilogHDL/test/Waveform.vwf --testbench_file=C:/VerilogHDL/test/simulation/qsim/Waveform.vwf.vt
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Completed successfully.
Completed successfully.
**** Generating the timing simulation netlist ****
quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="C:/VerilogHDL/test/simulation/qsim/" AlteraProject -c AlteraProject
Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
Info: Version 22.1std.1 Build 917 02/14/2023 SC Lite Edition
Info: Copyright (C) 2023 Intel Corporation. All rights reserved.
Info: Your use of Intel Corporation's design tools, logic functions
Info: and other software and tools, and any partner logic
Info: functions, and any output files from any of the foregoing
Info: (including device programming or simulation files), and any
Info: associated documentation or information are expressly subject
Info: to the terms and conditions of the Intel Program License
Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
Info: the Intel FPGA IP License Agreement, or other applicable license
Info: agreement, including, without limitation, that your use is for
Info: the sole purpose of programming logic devices manufactured by
Info: Intel and sold by Intel or its authorized distributors. Please
Info: refer to the applicable agreement for further details, at
Info: https://fpgasoftware.intel.com/eula.
Info: Processing started: Wed Jul 26 12:24:40 2023
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory=C:/VerilogHDL/test/simulation/qsim/ AlteraProject -c AlteraProject
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file AlteraProject_8_1200mv_85c_slow.vo in folder "C:/VerilogHDL/test/simulation/qsim//" for EDA simulation tool
Info (204019): Generated file AlteraProject_8_1200mv_0c_slow.vo in folder "C:/VerilogHDL/test/simulation/qsim//" for EDA simulation tool
Info (204019): Generated file AlteraProject_min_1200mv_0c_fast.vo in folder "C:/VerilogHDL/test/simulation/qsim//" for EDA simulation tool
Info (204019): Generated file AlteraProject.vo in folder "C:/VerilogHDL/test/simulation/qsim//" for EDA simulation tool
Info (204019): Generated file AlteraProject_8_1200mv_85c_v_slow.sdo in folder "C:/VerilogHDL/test/simulation/qsim//" for EDA simulation tool
Info (204019): Generated file AlteraProject_8_1200mv_0c_v_slow.sdo in folder "C:/VerilogHDL/test/simulation/qsim//" for EDA simulation tool
Info (204019): Generated file AlteraProject_min_1200mv_0c_v_fast.sdo in folder "C:/VerilogHDL/test/simulation/qsim//" for EDA simulation tool
Info (204019): Generated file AlteraProject_v.sdo in folder "C:/VerilogHDL/test/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
Info: Peak virtual memory: 4659 megabytes
Info: Processing ended: Wed Jul 26 12:24:41 2023
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:00
Completed successfully.
**** Generating the ModelSim .do script ****
C:/VerilogHDL/test/simulation/qsim/AlteraProject.do generated.
Completed successfully.
**** Running the ModelSim simulation ****
c:/intelfpga_lite/22.1std/questa_fse/win64//vsim -c -do AlteraProject.do
Error.
------------------------------------------------------------------------------
I appreciate a little help. Thanks.
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Hi,
Tested without problem from my site check the screenshot and file attached. May be try to recreate the project.
Note 1: In vwf, goto Simulation -> Simulation Settings -> Timing Simulation Settings -> delete -novopt -> save.
Note 2: If you don't get output waveform, try to use older device because vwf is legacy simulator for older device.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer
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Any further update or concern from your side?

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