- 新着としてマーク
- ブックマーク
- 購読
- ミュート
- RSS フィードを購読する
- ハイライト
- 印刷
- 不適切なコンテンツを報告
Hi,
I try to simulate a design with the QuartusII simulator. Some of the signals are however synthesised away. I connect the signals to output pins and use the "Implement as Output of Logic Cell", "Add to Simulation Output Waveforms" and "Preserve Fan-out Free Register Node". Does the signal have to be available at top-level in order to preserve the signal during simulation? It is test-signals on lower-level blocks, so I dont want to append the signal to the top-level. Hope someone can help. Regards, Mortenコピーされたリンク
4 返答(返信)
- 新着としてマーク
- ブックマーク
- 購読
- ミュート
- RSS フィードを購読する
- ハイライト
- 印刷
- 不適切なコンテンツを報告
"Preserve Fan-out Free Register Node" should be all you need (no need to route the signal to the top level) if you are using a device family supported by this assignment.
From QII 7.2 on-line help: --- Quote Start --- Preserve Fan-out Free Register Node logic option -------------------------------------------------------------------------------- This option can be set in the Assignment Editor. A logic option that specifies that the register should be preserved in the design even when it becomes fan-out free. This option is available for supported device (Arria GX, Cyclone II, Cyclone III, HardCopy II, MAX II, Stratix II, and Stratix III) families. --- Quote End ---- 新着としてマーク
- ブックマーク
- 購読
- ミュート
- RSS フィードを購読する
- ハイライト
- 印刷
- 不適切なコンテンツを報告
I have tried to put output pins on the lower-level blocks and set the Preserve Fan-out Free Register Node logic option without any luck. I also tried to look in the RTL viewer for the signal and assign the same option, but still the signals are no where to be found in the simulator.
I can only see them if I set the search option to "All name", but when I run the simulator they keep disappearing. Any thoughts?- 新着としてマーク
- ブックマーク
- 購読
- ミュート
- RSS フィードを購読する
- ハイライト
- 印刷
- 不適切なコンテンツを報告
--- Quote Start --- I have tried to put output pins on the lower-level blocks and set the Preserve Fan-out Free Register Node logic option without any luck. --- Quote End --- It should not matter whether the signal you want to preserve goes to an output port of an entity/module. It is necessary that the signal be a register.
- 新着としてマーク
- ブックマーク
- 購読
- ミュート
- RSS フィードを購読する
- ハイライト
- 印刷
- 不適切なコンテンツを報告
Now I found the problem. I mostly uses VARIABLES, but in order to use Preserve Fan-out Free Register it has to be SIGNALS.
Thanks for the help.