When you have vhdl with an error like:data(to_integer(index) to to_integer(index)+15)<="101010101010101"; (the right side is one bit short) Quartus stops but does not tell you why. I contacted Altera technical support, but as this problem only appears in the Lite version they won't fix it. So on your own trying to understand what crashed Quartus.:( Well... at least an internet search may help you now with this problem.
HiI don't know what version of quartus you are using. But in quartus 17, it says explicitly that the expression on the right side must have 16 elements. In verilog, this kind of assignment (the right side is lower/greater then the the left side) is allowed , although quartus reports some warnings related to truncation. --kais--