Source code assignments using altera_attribute

Altera_Forum · ‎07-27-2011

Can anyone tell me if it's possible to assign a different Stratix III D6_DELAY value to each member of an output buss in source code? I'm using Verilog.

It has to be in the source code because the project I'm dealing with uses a `define to select different configurations of/for the same project. The output delays depend on the particular configuration.

I've been trying to do something like this so far but without much luck:

(* altera_attribute = "-name D6_DELAY 5" *) output LVDS_TXD_PCB;

this is rejected but in any case would assign a global delay - I actually want a tailored delay per output.

Thanks,

Altera_Forum · ‎07-27-2011

Sorry line should have been:

(* altera_attribute = "-name D6_DELAY 5" *) output [63:0] LVDS_TXD_PCB;

but in any case it's still not accepted and not what I want...

Altera_Forum · ‎07-27-2011

Error was caused by a tab character so now to find out if I can tailor a delay per output from source code. Sorry for the sudden barrage of posts!

Altera_Forum · ‎07-27-2011

Problem solved I think. I used project revisions to create separate revisions of the build for each config. Settings could then be placed in the relevant qsf file.