Simulation in ModelSim Altera Starter Edition

Altera_Forum · ‎01-20-2011

Hi guys,

need a little bit help. I try ModelSim ALTERA STARTER EDITION 6.5b for the first time, have created a test project (two inputs, two outputs) and wanted to simulate it. My problem is – I can add my signals to the wave window, but I did not find a way to add a waveform to my signals in this window. I have used ModelSim SE PLUS before and in this program if I clicked with the right mouse button in the Objects window, I have got in the pull-up menu (upon other items) the “create wave” item. In the ModelSim Altera Starter Edition I see all these items too, except the “create wave” item. How can I add a waveform here?

Thank you

Altera_Forum · ‎01-20-2011

You have to drive signals from a testbench.

Altera_Forum · ‎01-20-2011

Tricky, thank you for your prompt answer.

Is it a extra limitation of ModelSim Altera Edition, that I have to obligatory use testbench and cannot add a waveform “on the fly” in the wave window?

Altera_Forum · ‎01-20-2011

I would recommend using a testbench to drive the inputs and to test the response of the outputs, but you could use the modelsim force command to drive your inputs.

Altera_Forum · ‎01-20-2011

I'm having the same problem described by the original post in this thread. I'm following the tutorial in Altera's ModelSim_GUI_Introduction.pdf and cannot access the "create wave" menu selection.

How do I create a testbench?

Altera_Forum · ‎01-20-2011

i think the Waveform Editor was only enabled in the latest ModelSim-A(S)E included with ACDS 10.1, version 6.6c

Altera_Forum · ‎01-21-2011

A testbench is just an HDL text file with signals to drive your unit under test. Simply instantiate your UUT, and create some behavioural signals. for example, to generate a clock in VHDL, you can simply do this:

signal clk : std_logic := '0';

...

clk <= not clk after 10 ns; --100 MHz clock.

and for stimulus:


process
begin
  input <= 0;
  wait for 100 ns;
  input <= 1;
  wait for 500 ns;
  input <= 2;
  for 1 in 1 to 20 loop
    wait until rising_edge(clk);
  end loop;
  input <= 3;
  wait;
end process;

This is just the tip of the iceburg

Altera_Forum · ‎01-21-2011

I'm using ModelSim 6.5b. So I won't be able to use the waveform editor at all in this version?

Altera_Forum · ‎01-21-2011

no, i don't think so

try Quartus II 10.1 and ModelSim 6.6c

Altera_Forum · ‎01-21-2011

and i agree about HDL test benches being proper work around. they aren't that bad :)

built a few templates (clocks, resets, from text file, to text file) and build test benches from the templates

Altera_Forum · ‎01-24-2011

Hi thepancake,

test benches are surely a good workaround and surely the most certain way to simulate a design, but sometimes one needs an opportunity for quick test without to have to write a new test bench. It is really a pity, that this feature is not implemented.

Apropos the test benches. I tried the following test bench with Quartus 9.1 SP2 :

---------------------------------------

library ieee ;

use ieee.std_logic_1164.all;

use ieee.numeric_bit.all;

use ieee.std_logic_unsigned.all;

use ieee.std_logic_textio.all;

use ieee.std_logic_arith.all;

use ieee.numeric_std.all;

library lpm;

use lpm.lpm_components.all;

library altera;

use altera.altera_primitives_components.all;

----------------------------------------

entity testbench_1 is

end testbench_1;

----------------------------------------

architecture test_1 of testbench_1 is

signal d : std_logic_vector(3 downto 0);

signal q : std_logic_vector(1 downto 0);

begin

dut: entity work.mv78200(behv1)

port map(d, q);

stimulus : process is

begin

d(0) <= '0';

d(1) <= '0';

d(2) <= '0';

d(3) <= '0';

wait for 500ns;

d(0) <= '1';

d(1) <= '1';

d(2) <= '1';

d(3) <= '1';

wait;

end process stimulus;

end architecture test_1;

and I got again and again the error message:

error (10533): vhdl wait statement error at testbench_1.vhd(43): wait statement must contain condition clause with until keyword.

(Line 43 is the statement "wait for 500ns;")

With ModelSim Altera Edition I can use this test bench without any problems. Any ideas?

Altera_Forum · ‎01-24-2011

You cannot compile test benches with quartus. Quartus only understands the "wait until" command for synthesising code. Test benches cannot be synthesised.

Secondly, do not use std_logic_arith and numeric_std in the same file.

Altera_Forum · ‎01-24-2011

Tricky, thanks for your information about Quartus.

You are right, it is not a good idea to use std_logic_arith and numeric_std together (have overlooked it as I copied parts of two different designs)

Altera_Forum · ‎02-16-2011

--- Quote Start ---

no, i don't think so

try Quartus II 10.1 and ModelSim 6.6c

--- Quote End ---

Hello, I continue with this topic while my question is the same.

How can I use the waveforme editor with modelsim 6.6d ? I've tryed with the example (counter.v) but I cannot change the waves.

Altera_Forum · ‎07-27-2011

Hello all,

I am new to this software and trying to learn in my free time.

Can anyone tell me how to setup modelsim on Quartus -II? I have tried to follow the steps from the pdf file provided,but I cannot see the option of settings in bold under Assignment.

Is there any way I can open Modesim once I download Quartus-II?

Thanks

Altera_Forum · ‎07-27-2011

Thanks all.

I finally figured it out to open Modelsim.