Source synchronous input clock and no output clock constraints

Altera_Forum · ‎09-26-2013

For my Stratix V design, a source synchronous, 4ns period, input clock is used to clock input data. The output data is clocked out of the FPGA back to the source clock without a TX clock. The external device's clock is used. Below are my timing constraints.

create_clock -name rx_phy_pipe_clk -period 4 [get_ports {rx_phy_pipe_clk}]

derive_pll_clocks

derive_clock_uncertainty

# virtual clock - source clock

create_clock -name rx_phy_pipe_clk_ext -period 4.0

set_input_delay -clock { rx_phy_pipe_clk_ext } -max 0.8 [get_ports {phy_mac_*}]

set_input_delay -clock { rx_phy_pipe_clk_ext } -max -0.8 [get_ports {phy_mac_*}]

set_output_delay -clock { rx_phy_pipe_clk_ext } -max 1.7 [get_ports {mac_phy_*}]

set_output_delay -clock { rx_phy_pipe_clk_ext } -min -0.1 [get_ports {mac_phy_*}]

From TimingQuest, I get setup violations to rx_phy_pipe_clk_ext. The data arrival path is 5.809ns (3.008 clock and 2.801 data) and data required path is 2.240ns. I believe I need to add a negative phase shift to reduce the clock delay on the data path. I've tried this but then I get failures elsewhere. Do I need to add multi-cycle path constraint on both inputs and outputs?

Any help is much appreciated!

Altera_Forum · ‎09-26-2013

If you do a negative phase-shift you probably need a multicycle. For example, if your PLL generated clock is 4ns just like rx_phy_pipe_clk_ext, then the setup relationship is 4ns and hold is 0ns. If you phase-shift the source clock by -250ps, then your default setup relationship is 250ps and your hold is -3.75ns. You probably want a multicycle saying you are targeting the next latch clock:

set_multicycle_path -setup -from [get_clocks <pll_clk_name>] -to [get_clocks rx_phy_pipe_clk_ext] 2

In the case above, that would made the setup relationship 4.25ns and the hold relationship 0.25ns.

Altera_Forum · ‎09-26-2013

What if I use a large phase shift like -3 ns? Also, would I need a multicycle on the input side as well?

Altera_Forum · ‎09-26-2013

Please look at the TimeQuest User , specifically default relationship and multicycles:

http://www.alterawiki.com/wiki/category:design_entry_and_optimization

In quick, your default setup relationship is the tightest latch - launch edge that is greater than 0. So with my example of -250ps shift, on the input side you probably don't need a multicycle because your setup relationship is 3.75ns and your hold is -0.250ps. If you draw out the waveforms, you can usually see it pretty quickly. If you're ever unsure what the setup or hold is, just run report_timing in TimeQuest and it will tell you the setup and hold relationship that it calculates.

If you do -3ns, and add a multicycle on the output, then your setup relationship is 7ns and hold is 3ns. That starts getting tight because your delay has to be greater than 3ns on the fast corner and less than 7ns in the slow corner. Probably do-able, but it gets tight. (My general rule of thumb is that the slow corner is 2x the fast corner delay).

With a -3ns shift, your setup relationship will be 1ns and hold of -3ns, so you probably do want a multicycle there. I don't know the exact delays you're dealing with, so it's hard to say.

Also note that you can have another output of the PLL. So you might have the input and core logic running off your existing clock, and then at the end transfer it to another tap of the PLL that has a phase-shift. That way you can separate your input timing from your output timing.

Altera_Forum · ‎09-26-2013

--- Quote Start ---

set_input_delay -clock { rx_phy_pipe_clk_ext } -max 0.8 [get_ports {phy_mac_*}]

set_input_delay -clock { rx_phy_pipe_clk_ext } -max -0.8 [get_ports {phy_mac_*}]

--- Quote End ---

is that -max twice a typo?

Altera_Forum · ‎09-26-2013

Yes a typo. It's really - min.

Below is from TQ for the failing output path. All other constraints are met. How do I resolve this without breaking the others?

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Data Arrival Path ;

+----------+----------+----+------+--------+----------------------------+-------+----------------------------------------------------------------------------------------------+

; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ;

+----------+----------+----+------+--------+----------------------------+-------+----------------------------------------------------------------------------------------------+

; 0.000 ; 0.000 ; ; ; ; ; ; launch edge time ;

; 3.008 ; 3.008 ; ; ; ; ; ; clock path ;

; 0.000 ; 0.000 ; ; ; ; ; ; source latency ;

; 0.000 ; 0.000 ; ; ; 1 ; PIN_BA27 ; ; rx_phy_pipe_clk ;

; 0.000 ; 0.000 ; RR ; IC ; 1 ; IOIBUF_X62_Y0_N45 ; ; rx_phy_pipe_clk~input|i ;

; 0.535 ; 0.535 ; RR ; CELL ; 10 ; IOIBUF_X62_Y0_N45 ; ; rx_phy_pipe_clk~input|o ;

; 2.367 ; 2.413 ; RR ; IC ; 1 ; DDIOOUTCELL_X94_Y0_N15 ; ; pcie_x1_top_Inst|mac_phy_txdata_r_0_|clk ;

; 3.008 ; 0.641 ; RR ; CELL ; 1 ; DDIOOUTCELL_X94_Y0_N15 ; ; pcie_x1_top:pcie_x1_top_Inst|mac_phy_txdata_c_0 ;

; 5.809 ; 2.801 ; ; ; ; ; ; data path ;

; 3.008 ; 0.000 ; ; uTco ; 1 ; DDIOOUTCELL_X94_Y0_N15 ; ; pcie_x1_top:pcie_x1_top_Inst|mac_phy_txdata_c_0 ;

; 3.291 ; 0.283 ; FF ; CELL ; 1 ; DDIOOUTCELL_X94_Y0_N15 ; ; pcie_x1_top_Inst|mac_phy_txdata_r_0_|q ;

; 3.291 ; 0.000 ; FF ; IC ; 1 ; IOOBUF_X94_Y0_N2 ; ; mac_phy_txdata_out_0_|i ;

; 5.809 ; 2.518 ; FF ; CELL ; 1 ; IOOBUF_X94_Y0_N2 ; ; mac_phy_txdata_out_0_|o ;

; 5.809 ; 0.000 ; FF ; CELL ; 0 ; PIN_BC25 ; ; mac_phy_txdata[0] ;

+----------+----------+----+------+--------+----------------------------+-------+--------------------------------------------------------------------------------------------+

+---------------------------------------------------------------------------------+

; Data Required Path ;

+---------+---------+----+------+--------+----------+-------+---------------------+

; Total ; Incr ; RF ; Type ; Fanout ; Location ; HS/LP ; Element ;

+---------+---------+----+------+--------+----------+-------+---------------------+

; 4.000 ; 4.000 ; ; ; ; ; ; latch edge time ;

; 4.000 ; 0.000 ; ; ; ; ; ; clock path ;

; 4.000 ; 0.000 ; R ; ; ; ; ; clock network delay ;

; 3.940 ; -0.060 ; ; ; ; ; ; clock uncertainty ;

; 2.240 ; -1.700 ; F ; oExt ; 0 ; PIN_BC25 ; ; mac_phy_txdata[0] ;

+---------+---------+----+------+--------+----------+-------+---------------------+

Thanks!

Altera_Forum · ‎12-26-2013

--- Quote Start ---

For my Stratix V design, a source synchronous, 4ns period, input clock is used to clock input data. The output data is clocked out of the FPGA back to the source clock without a TX clock. The external device's clock is used. Below are my timing constraints.

create_clock -name rx_phy_pipe_clk -period 4 [get_ports {rx_phy_pipe_clk}]

derive_pll_clocks

derive_clock_uncertainty

# virtual clock - source clock

create_clock -name rx_phy_pipe_clk_ext -period 4.0

set_input_delay -clock { rx_phy_pipe_clk_ext } -max 0.8 [get_ports {phy_mac_*}]

set_input_delay -clock { rx_phy_pipe_clk_ext } -max -0.8 [get_ports {phy_mac_*}]

set_output_delay -clock { rx_phy_pipe_clk_ext } -max 1.7 [get_ports {mac_phy_*}]

set_output_delay -clock { rx_phy_pipe_clk_ext } -min -0.1 [get_ports {mac_phy_*}]

From TimingQuest, I get setup violations to rx_phy_pipe_clk_ext. The data arrival path is 5.809ns (3.008 clock and 2.801 data) and data required path is 2.240ns. I believe I need to add a negative phase shift to reduce the clock delay on the data path. I've tried this but then I get failures elsewhere. Do I need to add multi-cycle path constraint on both inputs and outputs?

Any help is much appreciated!

--- Quote End ---

It seems to me, that the following line is missing: set_clock_groups -exclusive -group {rx_phy_pipe_clk rx_phy_pipe_clk_ext}

P.S. Did You solve Your problem?