I have a logic , where I have used 624 9x9 multipliers.
Device used - cyclone V GT( It has 342 DSP with each DSP having three 9x9 multipliers).
Fitter couldn't merge these 9x9 multipliers into a single DSP.It used to fail giving error as overuse of DSPs. So, I used logic lock to fit this Logic by randomly giving width and height( with specific number of DSPs resources).
Now , there was no fitter error .Before doing logic lock clock frequency achieved was 250 Mhz. After logic lock it dropped to 200 Mhz.
When I checked timing analyzer, critical path shown is in internals of lpm_mult IP. Note that I have registered input before passing to multipliers , and the output latency is also 3 clock cycles. So , ideally I should achieve max frequency of multipliers i.e, 300MHz. But it is not even meeting 200 MHz ( I feel it is because of logic lock).
Please answer below queries related to logic lock:
1) What is the correct way to select width and height of logic lock region?Please share some example design/ pdfs which describes how to work with chip planner and logic lock in detail?
2) How to achieve optimum frequency in logic locked region?Is there a way to give timing constraints separately for logic lock region?
First of all, thank you for reaching us,
I'm Eliath Guzman and I'll be attending your case.
I've already read the issue you have.
Could you tell me which version of Intel Quartus Prime Software are you using?
Please give me a day to share with you the proper documentation regarding your queries above.
I'm so sorry for that, please try what I recommend below and let me know any result you get.
I recommend setting the DSP usage for that module so, please try the following:
- Right-click on the module in the hierarchy and choose Local Node and then Assignment Editor
- once you are there, click on new, and in the row of the new assignment click <new> under Assignment name and select the Maximum DSP block usage.
- Put the expected number of DSP blocks to be used in the value column.
- Finally, select save and compile, and test again your project.
Regarding some documentation in case you still wanted to use logic lock regions, I add the link to a Chip Planner video-training which shows the correct way to create logic lock regions, this starts at minute 19:46.
It is important to mention that packing the DSP's is going to reduce the Fmax.
You will have area reduction or Fmax, but not both.
Setting separate timing constraints for logic lock region is not possible but what you can do is to create a design partition in that specific region and apply different settings to help with timing.
maybe this link can be helpful if you consider to use incremental based timing closure.
Please let me know all question you may have.
I'm concern about the status of the issue you shared with us, did my last answer solve it?
Do you have any questions?
Is there anything else I could help you with?