Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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State Machine File Tutorial??

Altera_Forum
Honored Contributor II
‎04-14-2011 04:12 PM
2,391 Views

Hi, 

 

I'm new to using State Machine Files for design. Creating the FSM was easy, but I want to compile and implement. I'm using Quartus 9.0 with DE2 Boards. I have questions: 

 

1) Is there a tutorial walking you though designing and implementing using .smf? 

 

2) If I want to use both .smf and .bdf files in my project, how do I connect it all together? 

 

thanks
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Altera_Forum
Honored Contributor II
‎04-15-2011 03:34 AM
1,572 Views

The Quartus II software saves the state machine diagram as a State Machine File (.smf). After defining the state machine logic, you can create a Verilog HDL or VHDL design file by clicking the Generate HDL File icon. You can then instantiate the state machine in your design using any design entry language.

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