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State machine fail to hold default value

Altera_Forum
Honored Contributor II
1,860 Views

Hi, all 

 

Here's example of my state machine coding in verilog:  

 

 

--- Quote Start ---  

always @(posedge clkADC or posedge RST) 

begin 

if (RST) 

state <= s0; 

else  

case (state) 

s0: if (START) state <= s1; else state <= s0; 

s1: ns <=s2; 

s2: ns <=s3; 

s3: ns <= s0; 

endcase 

end  

 

always@(state, DataIn) 

begin 

case (state) 

s1:begin 

fifo_wreq <= 1; 

Data <= DataIn;  

end  

s2:begin 

Data <= DataIn; 

end 

s3:begin 

Data <= DataIn; 

fifo_wreq <= 1; 

end 

default:begin 

Data <= 12'b000000000000;  

fifo_wreq <= 0; 

end 

endcase 

end  

 

--- Quote End ---  

 

 

fifo_wreq at s2 suppose to be default value, which is 0. However, I found out that it remain 1 at state machine s2. May I know any mistake i do so far?
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Altera_Forum
Honored Contributor II
659 Views

You didnt assign it to 0 in s2. In the second always block, you need to assign all values in all states. 

S1 will occur before s2, therefore fifo_wreq has already been set to 1 in the previous state. You created a latch (which is not a good thing) but letting it remember it's value between states.
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Altera_Forum
Honored Contributor II
659 Views

Hi, Tricky 

 

Thanks for reply. For my understanding, if I didn't assign fifo_wreq to 0 in s2, suppose fifo_wreq value is followed by the default value as stated 0. Am I right? 

 

May I know how to prevent the latch happen?
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Altera_Forum
Honored Contributor II
659 Views

 

--- Quote Start ---  

Hi, Tricky 

Thanks for reply. For my understanding, if I didn't assign fifo_wreq to 0 in s2, suppose fifo_wreq value is followed by the default value as stated 0. Am I right? 

 

--- Quote End ---  

 

 

No, once you assign a value to a variable, it stays at that value until it is assigned again 

 

 

 

--- Quote Start ---  

May I know how to prevent the latch happen? 

--- Quote End ---  

 

 

Ensure all variables are assigned in all cases in non-clocked always blocks. They should preferably be assigned with non-blocking assignments..
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Altera_Forum
Honored Contributor II
659 Views

 

--- Quote Start ---  

No, once you assign a value to a variable, it stays at that value until it is assigned again 

 

 

 

 

Ensure all variables are assigned in all cases in non-clocked always blocks. They should preferably be assigned with non-blocking assignments.. 

--- Quote End ---  

 

 

Variables in a non-clocked always block should be assigned with blocking assignments. 

Clocked always blocks should use non-blocking assignments.
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