Store complex decimal values as 2D array in a rom in verilog

Altera_Forum · ‎08-26-2016

I need to perform convolution between 2 matrices in verilog : a 7x7 matrix that holds complex double values and a 72x300 matrix that stores double values.

How should I store such a matrix in rom? Also creating 72x300 matrix involves storing large number of coefficients.

I am not able to understand how to initialize them and use them to perform convolution.

Please help!

Altera_Forum · ‎08-30-2016

--- Quote Start ---

I need to perform convolution between 2 matrices in verilog : a 7x7 matrix that holds complex double values and a 72x300 matrix that stores double values.

How should I store such a matrix in rom? Also creating 72x300 matrix involves storing large number of coefficients.

I am not able to understand how to initialize them and use them to perform convolution.

Please help!

--- Quote End ---

Is there no solution ? Please help..

Altera_Forum · ‎08-30-2016

What exactly are you having problems with? Have you even attempted to write any code?

Altera_Forum · ‎08-31-2016

My query is how to build a matrix in verilog? without which how can i perform convolution?

Altera_Forum · ‎10-03-2016

If you have a verilog or VHDL file opened in Quartus you can try inserting a ROM template that will drop in code that implements a ROM. If I remember correctly it's under "edit" --> "template"

Altera_Forum · ‎10-04-2016

For a 72x300 matrix you could use a rom with 128 by 512 addresses (64k). The Upper 7 bit is your first axis, the lower 9 addresses is your second axis in this case.

Depending on the data width this will be a big RAM, at least for a FPGA onchip Memory.

Assuming that your double value has 64bit you need 512kByte.

The 7 by 7 matrix needs 64 adresses with 128bit each:


module array (
		input   x_i,
		input   y_i,
		output  re_o,
		output  im_o
	);
	reg  array;
	initial
	begin
		array = {64'h00000000deadbeef, 64'h00000000affedead};
		array = {64'h0000000000000000, 64'h0000000011111111};
		array = {64'h0000000011111111, 64'h0000000022221111};
	end
	assign re_o = array;
	assign im_o = array;
	
endmodule

Though i don't know your exact requirements i would recommend to use the Altera altsyncram with a initialization .mif File. And a big enough FPGA.