Strange Modelsim simulation result (undefined).

[Altera_Forum]

I got a strange simulation result. 

Asserting Output in the simplest way    MostSignificant(MSA) <= VectorOnes (MSA); -- MostSignificant(MSA) is output   -- VectorOnes (MSA) in input   The result in the simulation is undefined.  -- Work around like that gets a reasonable result.   PROCESS (VectorOnes) Variable MostSignificantMSA : STD_LOGIC ;   BEGIN MostSignificantMSA := VectorOnes (MSA); MostSignificant(MSA) <= MostSignificantMSA;   Who does know why the simplest way doesn't work?

[Altera_Forum]

If you put the simple assignment in your process (rather than using a variable) it should also function correctly. 

 If you leave it outside the process (as commented out in your code) then I believe you might get contention. The process is driving the MostSignificant vector and so is the concurrent assignment. That said it does appear that the MSA bit is not driven in the process!   Simplest solution is to always drive the entire vector from the same process i.e. simplify the code to   PROCESS (VectorOnes)  BEGIN MostSignificant(MSA) <= VectorOnes (MSA);

[Altera_Forum]

Dear Vernmid  

Thank you for your answer. When I put the simple assignment in the process as you suggest I got in the simulation undefined in the two first cycles and amazing in the other cycles the value of MostSignificant(MSA) was as the VectorOnes (MSA) in the previous cycle. I know it shouldn't happen according to VHDL instruction.   In all the versions MostSignificant(MSA) is assigned only once.   My amazement is because according to VHDL I shouldn't get any problem in both versions when the assignment is out the process and in the process.   Best Regards Rami