Strange problem with EPCS

Altera_Forum · ‎08-26-2011

I have a strange problem with EPCS on one of my custom boards.

The device is connected to a EP3C40 fpga and I program it using Quartus programmer and SFL. I have a .jic file for this.

The problem is: programmer stops with an error, it seems during erasing step

Info: Erasing ASP configuration device(s)
 Error: Operation failed
 Info: Ended Programmer operation at Fri Aug 26 11:47:04 2011

Sometimes it seems jtag can load not even the SFL image:

Info: Started Programmer operation at Fri Aug 26 12:00:13 2011
Info: Configuring device index 1
Info: Device 1 contains JTAG ID code 0x020F40DD
Info: Configuration succeeded -- 1 device(s) configured
Error: Flash Loader IP not loaded on device 1
Error: Operation failed
Info: Ended Programmer operation at Fri Aug 26 12:00:16 2011

I have another identical board which I can program successfully in this way.

So I thought there was some problem with the board itself. I tested epcs signals but I can't see nothing wrong.

And now the weird part:

The Nios configured in my fpga features epcs programming capabilities, since this is used for remote update and for storing application data. Then I loaded the application with jtag and then I used Nios to program epcs: this way it works perfectly and I can erase/program it without errors.

AFAIK the only difference is that my Nios application doesn't touch the first sectors where the factory image is stored, namely the area which .jic file is supposed to load.

However epcs signals are still the same, so I'd exclude a problem on the pcb or with the epcs itself.

Any hints will be greatly appreciated. Thank you.

Altera_Forum · ‎08-26-2011

My first guess is check the clock signal integrity.

If you don't have a source resistor on on the Active Serial programming connector, you can change the source resistor inside the usb-blaster. (If that's the programmer you are using)

By default it has a 10 ohm source resistor. I have modified ours with a 22 ohm, which seems to make it much more robust on on variety of boards.

Pete

Altera_Forum · ‎08-29-2011

I do have source resistor. The problem seems not related to signal integrity, but to Altera Serial FlashLoader used by .jic to bridge data inside CIII between jtag and epcs interfaces.

Infact I can reprogram epcs effectively if I use my fpga configuration and nios2-programmer

Cris