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Stratix IV DDR clock constrain problem

Altera_Forum
Honored Contributor II
‎09-21-2012 02:36 AM
1,002 Views

Hi friends,  

 

I am working on a DDR project in Stratix IV FPGA. I am using ALTMEMPHY. Now I get a problem that the FPGA cannot work stably. Note that I make a clock constrain for DDR input clock pin and there is a conflict warning for this clock constrain and DDR PHY sdc file. Is this the root cause? And I shall not use this clock input frequency constain in the top sdc file and just use PHY sdc file?  

Thanks!
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