Stratix IV PLL limits

[Altera_Forum]

Hi: 

 I have a 2 fpga stratix iv board and I want to generate a 1 MHz synchronous clock in both. When I use the PLL, quartus refuses to let me give a clock slower than 5MHz to the PLL. How can I do this with a PLL?  thanks.

[Altera_Forum]

Just use a fast clock and divide the output with FPGA hardware to whatever speed you need. Discrete flip-flops, lpm functions, etc., lots of ways to generate a slow clock.

[Altera_Forum]

Unfortunately this is not possible. StratixIV has a lower PLL input limit of 5MHz. The only option would be to use an external PLL which will handle this frequency. 

 What exactly are you wanting to do here? If you have a high frequency clock outside the FPGA, you could divide it down with the PLLs and use this as a system clock.  Best regards,  Steve

[Altera_Forum]

If I use a High frequency clock to the On chip Altera PLLs on the 2 fpgas and divide it down, 

will the generated clocks be in sync?

[Altera_Forum]

The basic answer is 'maybe', but there are several other things to consider.  

 (i) Where is the master clock sourced from? (ii) What is the frequency? (iii) Is the clock balanced between the two FPGAs? By this, I am asking whether the trace lengths are the same so that the time it takes the clock to arrive at each FPGA is the same (iv) When you ask if the clocks will be in sync, what you are really asking is whether the clocks will be in phase. There will always be some phase difference - how much are you able to tolerate?  If you could explain exactly what you are trying to do, that would help.

[Altera_Forum]

hi stephen, many thanks. the clocks are balanced, very little skew. i am passing 

a master clock 5 mhz to both the fpgas. The phase difference is exactly my quesiton. If i use a pll to divide, will the derived clocks drift too far over the run?

[Altera_Forum]

To answer your question: "If i use a pll to divide, will the derived clocks drift too far over the run?" 

 By definition, PLLs do not drift - their goal is always to keep edges phase aligned. However, they do have some level of jitter, which is dependent upon many factors and could be 100's of ps or more depending upon their configuration and source clock.  At 5MHz, you have a period of 200nS. With a period this large, the overall jitter will account for a very small percentage of phase difference between the clocks. How much phase mis-match can you tolerate in your design?