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YTLim
Employee
195 Views

Stratix V programming files problem - SOF file ok but POF file not working

I have weird issue where the programming SOF file is working but the POF file is not working. I am currently working on a Stratix V device (5SGXMA3K3F40C4) .

All my previous programming files were both working before this, where after programming using the blaster via JTAG port as well as to the SPI (EPCQ256) chip, they work just fine.

I have been changing the Verilog codes substantially recently and was testing my codes through the SOF programming without issues until I tried programming the SPI chip using the POF file. The programming through the USB blaster worked without a hitch however, my whole system could not function at all using the POF file. SOF programming is still ok.

Further debug found that there is a link to how many FIFO I instantiate in my design. Currently it has >32 FIFO instantiated. When I cut the number of FIFO instantiation to about 4 or 5. The POF works again???

What is happening here?

 

18 Replies
NurAiman_M_Intel
Employee
171 Views

Hi,


Thank you for contacting Intel community.


What Quartus version did you use to run the FPGA?


Regards,

Aiman


YTLim
Employee
163 Views

Hi Aiman,

The Quartus version I was using is 18.0.0 Build 614 04/24/2018 SJ Standard Edition

 

I have even tried older version of quartus (16.0) and it was also giving me the same issue.

Rgds,

YT

NurAiman_M_Intel
Employee
156 Views

Hi,


It is odd for POF to not working while SOF is working. Please be noted that I am checking this with my team. I will get back to you on Friday.


Thanks.


Regards,

Aiman


NurAiman_M_Intel
Employee
141 Views

Hi YT,


Can you share with us your error message?


Regards,

Aiman


YTLim
Employee
134 Views

Hi Aiman,

There no error message.  I can successfully program the POF file into the SPI chip. Just that after programming the POF file into the SPI chip, my system just hang and not working. If I program it directly into the FPGA using the SOF file, my system worked as intended.

If you like we can have a remote debug session and I can show you the behavior.

Rgds.

NurAiman_M_Intel
Employee
131 Views

Hi,


May I know how is the system hang meant by? Is it during Quartus Programmer programming or the FPGA can be configured with the POF but the FPGA is not functioning at all after that?


Regards,

Aiman


 

 


YTLim
Employee
128 Views

Hi Aiman,

The FPGA is not functioning. That is why my system hang when I use POF file. Using the SOF file, the FPGA is working fine and my system fill function normally as per the Verilog design.

The funny thing is that, it will work fine using the POF programming if I change my Verilog codes from using 32 FIFOs to using only 3-4 FIFOs.

Rgds,

YT

NurAiman_M_Intel
Employee
118 Views

Hi YT,


Just to let you know that we are working on this issue internally. Will provide you update on this.

Appreciate your understanding.


Thanks.


Regards,

Aiman


YuanLi_S_Intel
Employee
109 Views

Hi YTLim,


There are few things that would like to check with you:

- May I know what is the failure rate? Does this issue happens on all the boards?

- What is the the type of SPI flash used in the board?

- Have you try to unload the content program into the SPI flash and compare it with the original file to make sure the content stored in SPI flash is not corrupted?

- After configuration, you mentioned that the device hang and is not functioning, can you probe the "CONF_DONE" pin? Is it in HIGH state?


Thank You.


YTLim
Employee
106 Views

Hi YuanLi

To answer some of you questions

Failure rate is 100%. Failed on 3 systems that we have tried.

SPI flash chip is the Altera EPCQ256

No, we did not unload the program from SPI chip back to compare. Need get help from you guys on how to do that.

CONF_DONE signal was "low" when it fail with the bad version of the POF file. Other good version of the POF has the CONF_DONE signal "high".

Rgds,

YT

 

 

YuanLi_S_Intel
Employee
98 Views

Hi,


Another thing is that, the FIFO used, is it Intel PSG IP?

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf


Or it is just written by you in the design?


Thank You


YTLim
Employee
73 Views

Hi YuanLi,

The FIFO I use is PSG IP. I implement a 1x128k FIFO IP and instantiate 32 of them.

Rgds,

YT

 

YuanLi_S_Intel
Employee
70 Views

Hi YTLim,


Thanks for the update. Can you try to use "Examine" function on Quartus Programmer to read back the bitstream? Then compared the bitstream and let me know if there are any differences or not.


Thank You.


YTLim
Employee
61 Views

Hi YuanLi,

There are some differences near the beginning of the file and near the end of the file. Here is the compare. The reset of the compare is matching. I converted the compare to match the hex values.

-------------------------------------------------------------------------

Beginning Original POF file

0000080: 2300 0400 0000 4d14 0000 1100 0c00 0002  #.....M.........
0000090: 0000 0000 0000 0000 0010 0100 ffff ffff  ................

Beginning Examined POF file

0000080: 2300 0400 0000 0000 0000 1100 0c00 0002  #...............
0000090: 0000 0000 0000 0000 0010 0100 ffff ffff  ................

-------------------------------------------------------------------------

End Original POF file

2000090: ffff ffff ffff ffff ffff ffff 1a00 2600  ..............&.
20000a0: 0000 0000 0000 0000 d000 0000 0100 6d50  ..............mP
20000b0: 6167 655f 3020 3030 3030 3030 3030 2030  age_0 00000000 0
20000c0: 3344 3741 3835 383b 0800 0200 0000 202b  3D7A858;...... +
20000d0: 0a                                       .

End Examined POF file

2000090: ffff ffff ffff ffff ffff ffff 1a00 2700  ..............'.
20000a0: 0000 0000 0000 0000 d800 0000 0100 6d45  ..............mE
20000b0: 5043 5132 3536 2030 3030 3030 3030 3020  PCQ256 00000000 
20000c0: 3130 3030 3030 3030 3b08 0002 0000 00b7  10000000;.......
20000d0: 370a                                     7.

-------------------------------------------------------------------------

Rgds,

YT

YuanLi_S_Intel
Employee
52 Views

Hi YTLIM,


May i know how do you program the POF into the EPCQ flash? Do you use our quartus programmer or use own script? If you are using quartus programmer, how do you do the programming? What are the setting u chose?


Also, can you try to generate JIC from the SOF and then program it into the flash via our Quartus Programmer?


Thank You.


Regards,

Bruce


YTLim
Employee
50 Views

Hi YuanLi,

I use both Quartus programmer as well as my own script to program the EPCQ and both did not work with the "bad" compile POF files. Both programming method works when used with "good" compile POF file.

As for the Quartus programmer setting, I use the "Active Serial" setting to program in the POF file.

I tried converting SOF to JIC and try programming using the "JTAG" setting in the Quartus programmer but it did not work. I don't know if I did the conversion properly. This did not work for both the "good" and "bad" compiles.

I even tried to convert the SOF file to a POF file. This also did not work for both "good" and "bad" compiles. Again I don't know if I did the conversion properly as when I compare the converted POF file to the compiled POF file, there is a significant difference.

Rgds,

YT

YuanLi_S_Intel
Employee
47 Views

Hi Lim,


So the read back POF file is using Quartus Programmer with Active Serial Configuration Scheme right? Setting are the same for both read back and programming? Just want to make sure both topology are the same for valid bitstream comparison.


The "did not work" you mentioned when programming JIC using JTAG configuration scheme is not able to program the flash with failure or fail to configure the FPGA during bootup?


Can you share me the SOF file? i try to generate the JIC for you. And the flash is EPCQ256 right?


Thank You.


Regards,

YL


YTLim
Employee
42 Views

Hi YuanLi,

Yes both readback and programming is using "Active Serial"

The "did not work" means, the converted POF file or JIC file is able to be programmed using the Quartus programmer successfully. However the FPGA is unable to boot.

Please see attached file for the SOF file. I am using EPCQ256 chip to store the program. FPGA I am using is  "Stratix V"  5SGXMA3K3F40C4

Rgds,

YT