I am trying to synthesize a design which is relatively big with ~ 30k lines of RTL. But the process just get stuck at analysis and synthesis stage. I waited for more than 10 hours but had no luck. I have synthesized the same design before but it was working fine. But now I added new modules to the design and I am facing this error. There are no error or warning messages which infer non-synthesizable RTL in log files. I went through all the changes I did from previously synthesized RTL and everything was synthesizable (normal assign,always and generate blocks).
The last message that I see is "Inferred 1713 megafunctions from design logic" and "60 instances of uninferred RAM". I was getting the same message when the design was synthesizing properly but just 59 instances of uninferred RAM instead of 60.
Can anyone please help me with this? Have anyone faced this issue? Any help would be appreciated
Thanks and regards
How much compile time does it take if it can pass through? Can you share out the passing Fitter report to check the resource utilization in term of ALM and memory block? I suspect it may be running out of resource or congestion in some location.
Thanks for replying.
It was taking 4-5 hours to go till sign-off. I think resource utilization is not a problem, resource utilization was 18% for ALM's and 5% of BRAM. I have attached the reports for your reference. Also, design completed the synthesis after waiting for 2 days. I attached reports of both working and problematic designs.
The maximum processor is just 8 while the working design is 16. Increase it if possible to speed up the compile time. Observed that both of designs are not exactly the same, right? The resource utilization in non-working one are way more larger than the other. It used up 20% ALM, 26% M20K & 30% DSP( working design using 8% ALM, 19% M20K &15% DSP). From synthesis message, most of them are reporting inferring memory block where I guess it may be the reason taking longer time to synthesis. My advice is to lock down certain large module to post fit or try to replace some of them with RAM IP from IP catalog, see if it reduces some compile time.