Synchronization Chains not detected

[Altera_Forum]

Hi there, 

 I have clock domain crossing in my design. I use synchronization chains for metastability. In a part of my design I instantiate a custom made dual clock FIFO. After the flow is completed I receive timing violations @ the domain crossing signals !!! The strange point is that I looked into the metastability report in the compilation report, It reported me that there were no synchronization chains found. So, what I understand is that It did not see the register chains (I'm using chain length = 3) as synchronization chain.  I there any option in the tool that I must set ? This is very strange because I really used the same component before in other projects but this problem did not show up !  Thanks in advance.

[Altera_Forum]

You need to place the two clocks in different groups in the sdc file, so that Timequest understands that it doesn't need to follow any timing requirements at the junction between the two domains. I believe that once you do this, it will be automatically added to the metastability report.

[Altera_Forum]

I enabled some option in the sta options and it generated Metastability report. But I still get timing violations. The two clocks are generated from PLLs. In the sdc file I'm using the constraint : 

derive_pll_clocks -create_base_clocks Do I still need to constraint those two clock ?

[Altera_Forum]

Yes, you need to set them in two different groups. IIRC the command is set_clock_groups -asynchronous -group

[Altera_Forum]

I did not create groups for the two clocks in the sdc file. Should I first do that ? Then shall I use your command directly ?

[Altera_Forum]

This is very strange. I have a data bus from registers in domain clk250Mhz. Then I perform some logic function on the bus (combinational logic). The output processed bus is then entered to a synchronization chain clocked by the other clock clk200MHz. I receive a setup violation !! It seems like the tool does not understand that the register chain is for synchronization ! 

 Is this related to the missing constraint ?

[Altera_Forum]

Yes. By default Timequest will examine the relationship between all the signals, including those that come from different domains. You can restrict this by creating groups, and then Timequest will ignore all the signals crossing from one group to another. But of course this means that you need to be sure that ALL the signals that go from one group to the other are properly synchronized. 

So in your case, if you place the clk250Mhz in group A and clk200MHz in group b:set_clock_groups -asynchronous -group { clk250Mhz } set_clock_groups -asynchronous -group { clk200Mhz }You can put several clocks in the same group, for example if you have a 100MHz output coming from the same PLL than the 200MHz clock, and signals crossing from one to the other without synchronisation, replace the last line by:set_clock_groups -asynchronous -group { clk200Mhz clk100MHz}All the clocks that you use in your design should be in one group. At least for the sake of clarity, I don't know if Timequest places automatically all the remaining clocks in another group.

[Altera_Forum]

Many thanks.