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Synchronizing a state machine

Altera_Forum
Honored Contributor II
‎07-14-2016 08:32 AM
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Hi,

I've got a state machine in a component and there's something I don't understand correctly.

 

See attachments for code of the component and test bench.

 

I'd like everything of the s2 state to be done during s1. So I simply copied everything from line 130 to 161 between 126 and 127 but the simulation result is not what I expect: cur_blk isn't correct. Do I have a problem with th RAMs management?

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Altera_Forum
Honored Contributor II
‎07-14-2016 10:41 AM
634 Views

This is not something we can really do, because we have no idea about design intention. 

You need to get debugging in your simulator to see whats going wrong. Trace the problem back from where it starts.
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