SynplifyPro for .vqm then Quartus P&R - Can't compile duplicate entity

Altera_Forum · ‎07-31-2014

I'm using Synplify Pro which compiles my .VHDL file and several Altera IP cores. The output is a .VQM.

This is then input to Quartus for P&R. All scripts. quartus_sh is passed a .tcl file.

It gives several errors: "Can't compile duplicate declarations of entity " ... " into library "work".

Anyone know what's wrong?

I have a similar project with just one IP core and that synthesized OK. Scripts are the same except

for the added QIP files.

Thanks

Altera_Forum · ‎07-31-2014

A .qip file often compiles IP into different libraries. For example, if you create two DDR3 interfaces, they may both have a file called calibration.v(I'm making that up as an example). Now, in Verilog and VHDL you can't add two files with the same top level name. (They may be identical, but synthesis doesn't know that and doesn't check for it). Normally you would only add it once, but that would be a pain with IP, having to manage which files are duplicates from other IP and selectively removing them. The way it's handled is the .qip compiles them into libraries that match the IP name, so for example, you can have two distinct calibration.v files.

I'm guessing Synplify reads them in, but when it writes them into the .vqm it removes that separation. If you search the .vqm, are there more than one module with that name?

There are probably multiple ways to solve this, but I think the easiest would be to let Quartus synthesize the IP and just black-box it in Synplify.

Altera_Forum · ‎07-31-2014

--- Quote Start ---

A .qip file often compiles IP into different libraries. For example, if you create two DDR3 interfaces, they may both have a file called calibration.v(I'm making that up as an example). Now, in Verilog and VHDL you can't add two files with the same top level name. (They may be identical, but synthesis doesn't know that and doesn't check for it). Normally you would only add it once, but that would be a pain with IP, having to manage which files are duplicates from other IP and selectively removing them. The way it's handled is the .qip compiles them into libraries that match the IP name, so for example, you can have two distinct calibration.v files.

I'm guessing Synplify reads them in, but when it writes them into the .vqm it removes that separation. If you search the .vqm, are there more than one module with that name?

There are probably multiple ways to solve this, but I think the easiest would be to let Quartus synthesize the IP and just black-box it in Synplify.

--- Quote End ---

Thanks. That's exactly what I did. I have a .prj file that is input to Synplify Pro. For the IP cores one such line is:

add_file -vhdl -lib work "../source/pll0.vhd"

I had a line like this for all of the IP cores. I took them all OUT! Quartus synthesized OK.

So, if Synplify Pro is used for the synthesis part one does NOT include the IP cores? I have not found that expressed anywhere.

Altera_Forum · ‎07-31-2014

It's not a rule, but you have to manage which files get added and either make sure there are no repeats or handle them with libraries or something like that. I'm not sure if Synplify has any other ways to handle duplicates.