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Altera_Forum
Honored Contributor I
1,202 Views

Synthesis error in VHDL process

Hi, 

 

I am trying to implement clock synchronizer and clock divider in the following piece of VHDL code. The clocks(clk_rx and clk_tx) should synchronize at the rising and falling edges of 'RX' signal on the bus. I can simulate the following in Modelsim but it is not synthesizable in ISE since i am using " RX'EVENT ". Could any one suggest an alternative for this? (vhdl or verilog) 

 

 

-------------------------------------------- CLOCK DIVIDER---------------------------------------------------------------------------------------- 

 

 

 

 

PROCESS (CLK_I, RX) 

BEGIN 

IF (RX'EVENT) THEN 

clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);  

ELSIF (CLK_I'EVENT AND CLK_I = '1') THEN 

IF clk_cnt >2499 THEN 

clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);  

ELSE  

clk_cnt <= clk_cnt + 1;  

END IF; 

END IF; 

END PROCESS; 

 

 

 

clk_rx <= '1' WHEN clk_cnt = 1250 ELSE '0'; -----clk_rx=1 only at the half of the counter period----------clk enable 

clk_tx <= '1' WHEN clk_cnt = 2499 ELSE '0';
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3 Replies
Altera_Forum
Honored Contributor I
30 Views

you cant detect both edges of the RX signal, you are only allowed to detect a single rising or falling edge, and us it as the clock - not in addition to another clock.  

What is RX? is it really a clock or some other signal? usually you would create an edge detector by comparing a registered version of a signal to the signal itself.  

 

It simulates fine because lots of VHDL works fine in simulation but is no use for synthesis.
Altera_Forum
Honored Contributor I
30 Views

Thanks for the reply. RX is the receiver pin. I am implementing a protocol similar to CAN. The module is connected to wishbone bus. So CLK_I is wishbone clock. 

The specification says I should synchronize to both edges of RX. I have changed the code little bit to compare the registered version of RX. Is this what you mean? 

 

PROCESS (CLK_I) 

BEGIN  

IF (CLK_I'EVENT AND CLK_I = '1') THEN 

tmp_RX <= RX; 

IF (RX /= tmp_RX) THEN 

clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);  

ELSIF clk_cnt >2499 THEN 

clk_cnt <= to_unsigned(0,clk_cnt'LENGTH);  

ELSE  

clk_cnt <= clk_cnt + 1;  

END IF; 

END IF; 

END PROCESS;
Altera_Forum
Honored Contributor I
30 Views

thats much better, and should synthesise

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