I have the Stratix IV GX dev board and I'm working trying to build a fairly simple design, but I'm having trouble getting the pin constraints set properly.I started with the golden_top.qsf that's installed with the dev kit installer and modified the applicable signals for my design. The problem I'm running into is with DDR3 constraints that come straight from the golden_top.qsf file. Here's the first error followed by the constraints:
Error: Can't place node "ddr3top_ck_pn" -- node is a differential I/O node
set_location_assignment PIN_D24 -to ddr3top_ck_p set_location_assignment PIN_C24 -to ddr3top_ck_pn … set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3top_ck_p set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3top_ck_pn … set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3top_ck_p set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3top_ck_pnI tried commenting out the *_pn constraints and let the tool auto-assign them. That cleared up that error, but flagged the same error on the DQS constraints. I tried commenting out the *_pn constraints again, but now I get the following error:
Error: Pin ddr3top_dqs_p uses pseudo-differential output node vip_system:U_VIP_System|ddr3_mc_top:the_ddr3_mc_top|ddr3_mc_top_controller_phy:controller_phy_inst|ddr3_mc_top_memphy_top:memphy_top_inst|ddr3_mc_top_memphy:umemphy|ddr3_mc_top_new_io_pads:uio_pads|ddr3_mc_top_altdqdqs:dq_ddio.ubidir_dq_dqs|pseudo_diffa_0. However, these pins also have an I/O standard LVDS that cannot be supported by the pseudo-differential output node.Okay... so while trying to figure that one out, I came across this in the Quartus Help under altiobuf_out Megafunction:
Do not use pseudo-differential I/O standards such as differential SSTL or differential HSTL on an output or bidirectional pin with output enable or on-chip termination (OCT) control. The output-enable/OCT logic does not automatically duplicate to the n-pin and your design will not fit.So what's the correct way to constrain these pins? I would have thought the "golden" constraints file supplied with the dev kit would work!
Update:I found that the IO standard was incorrect and should be "DIFFERENTIAL 1.5-V SSTL CLASS I" for the DQS and CK signals. Interesting that the "golden" constraints file shipped with the dev kit is wrong... I'm still working through issues, but most of them stem from using and trusting that golden file. I followed the recommended process of running the auto-generated tcl script for DDR3 pin assignments and exported those assignments. I'm working through those to update my constraints file now. At least its progress. I'm still making the migration from many years with brand X to Altera. I'm finding lots of differences in methodologies between the two brands.
I had to blow away my constraints and run the pin assignments tcl script for the memory controller.The short answer is to *not* trust the "golden" QSF file. I also found incorrect pin assignments on the HDMI interface where some of the data lines were left unassigned. I ended up going through the pin tables and the dev board schematic and fixing all of the errors manually.
I have Arria II GX, device EP2AGX260FF35I3.Same crap with golden top assignments :-] Thanks guys, you saved me tons of time! If anyone out there is struggling with DDR3 for Arria II GX board, take a look at http://www.altera.com/support/examples/verilog/ver-a2gx-ddr3-altmemphy.html