Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Synthesis of Nios II Processor

Altera_Forum
Honored Contributor II
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Whenever Quartus II is compiling the design, it reports back some interesting things about the Nios II processor: 

 

warning (10335): unrecognized synthesis attribute "auto_dissolve" at std_1s40.vhd(63) 

- the line in question reads: attribute auto_dissolve of diag_port_uart_s1_arbitrator : entity is false; 

 

Another very peculiar message is this: 

 

info: elaborating entity "cpu_test_bench" for hierarchy "std_1s40:inst|cpu:the_cpu|cpu_test_bench:the_cpu_test_bench" 

 

Does the synthesis tool try to compile ALL VHDL files in the current directory, irregardless if the file is part of the design? The file is listed in the Files section in the Settings menu, but since I inherited this design, I have no idea if it's suppose to be listed or not. It seems to me that a TEST BENCH should never be listed as a design file, but since I'm still new at this, just thought I would ask the question.
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Altera_Forum
Honored Contributor II
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At least in the past, there was a file, probably your cpu_test_bench, that had both synthesis and simulation information. As I recall, only a tiny part of the file was needed for synthesis. I filed a request with Altera asking that the synthesis and simulation information be segregated in separate files. I didn't find my old request to check the status, but I doubt that anything has been changed.

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Altera_Forum
Honored Contributor II
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It's pretty hard to believe that any semiconductor would use a testbench file with synthesis commands in it, but I've heard of even stranger things before, so it doesn't suprise me. For now, I'll keep it in the list of required files for synthesis.

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Altera_Forum
Honored Contributor II
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Quartus II will analyze (parse) any file in the project files list. But it only elaborates something if it's part of the actual design hierarchy. I wouldn't study too critically the elaboration or synthesis of IP.  

 

The attribute warning you reference comes about because parts of the NIOS II code were originally developed using a third-party synthesis tool that supported such an attribute. However, QIS doesn't support the attribute, which should probably just be removed from the design files by whoever develops the NIOS II code. For now, you can simply ignore the warning.
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