Synthesis tool optimizing out block?

[Altera_Forum]

It appears as if the the synthesis tool has possibly optimized out a block in the design I am working with. When I run the Name Finder tool in TimeQuest using the get_keepers command, the tool does not report back a clock net for a generated clock in the hierarchy. In fact, it appears as if the clock generator block has been optimized out by the synthesis tool, but I cannot find a reference to this in the synthesis report. 

 The block in question is also used in another area of the design, so is there a command I need to set to tell Quartus II to specific instances of duplicate blocks? This would be similar to the uniquify command in Synopsys Design Compiler. If you've ever used Design Compiler FPGA, you might have used this command.

[Altera_Forum]

Quartus removed duplicate registers/logic by default. You can globally turn it off under Assignments -> Setting -> Analysis and Synthesis -> More Settings -> Remove Duplicate Registers = Off. I don't recommend doing this globally, as most designs have some replication they don't know about and don't want. But you can also do it on a hierarchy or register level. For a hierarchy, right-click on it in the Hierarchy Browser and Locate -> Assignment Editor. Then in the Assignment find Remove Duplicate Registers and set it to Off. You can also just open the assignment editor and find registers directly in the To Column(Double Clock on an empty row in the To column, and an arrow will show up, taking you to the Node Finder). I do this when manually replicating logic to meet timing(I change it in the code and do it here.) You can also make these assignments directly in the code via comment/pragmas, but I prefer doing it in the .qsf since it is an Altera specific command.

[Altera_Forum]

--- Quote Start ---  For a hierarchy, right-click on it in the Hierarchy Browser and Locate -> Assignment Editor. Then in the Assignment find Remove Duplicate Registers and set it to Off  --- Quote End ---    Is there a specific category in the Assignment editor that I should be looking for? So far, I don't see a listing for "Remove Duplicate Registers" in the Assignment Editor.

[Altera_Forum]

it's in the drop-down list when you select Edit Cell in Assignment Name field context menu.

[Altera_Forum]

I discovered this soon after I placed the last post. In addition to Remove Duplicate Registers - OFF, I also set Remove Redundant Logic Cells - OFF. After I did this, and then reran the compilation, the synthesis tool reported it was elaborating the instance that was being removed. So this command definitely worked. 

 thanks to everyone for the support!

[Altera_Forum]

--- Quote Start ---  When I run the Name Finder tool in TimeQuest using the get_keepers command, the tool does not report back a clock net for a generated clock in the hierarchy. In fact, it appears as if the clock generator block has been optimized out by the synthesis tool, but I cannot find a reference to this in the synthesis report.  --- Quote End ---     I know you've solved the problem that started this thread, but here are suggestions for finding clocks.  The Fitter compilation report lists clocks at "Resource Section --> Control Signals". I sort the table by clicking the "Usage" column header to list all the clocks together. These clock signals might not correspond exactly to the signal TimeQuest considers to be a clock. For example, a clock driven by a register followed by a LUT will have the LUT signal name in the Fitter report but the register name in the TimeQuest reports. The Fitter's list of clocks is good to look at to see which signals are directly driving the clock input pins of registers. This is one way to find things like unintended gated clocks, which TimeQuest doesn't report. (TimeQuest reports ripple, or register-driven, clocks but not gated clocks.)  To find the TimeQuest name of a clock signal that is not yet constrained, there are a couple of reports you can use.  "Report Unconstrained Paths" (report_ucp) will list unconstrained clocks in the "Clock Status Summary" table.  "Check Timing" (check_timing) will list unconstrained clocks in the "No Clock" table. The clock signals will be the rows with this in the "Reason" column: "Node was determined to feed a clock port but was found without an associated clock assignment."

[Altera_Forum]

You could also use the report_clocks command.....but I haven't tried this yet, so I'm not sure what data TimeQuest will give you. Currently, I am using TimeQuest to read in the netlist and SDC file, and then looking at the initial report to see what clocks have not been constrained. This is a good starting point for me since I am not intimately familar with the design. 

 I've used the Fitter report in the past, but didn't think about using it for the clock resources. But I'd rather use TimeQuest to give me the info, since I'm using information supplied by that tool to properly constrain the clocks. But you do bring up a good point, something that I need to think about after I finish editing the SDC file. The Fitter as well as TimeQuest reads in the SDC file, so it's important that the contrainst will apply to both tools.

[Altera_Forum]

report_clocks does not list unconstrained clocks. 

 The Fitter needs the clocks constrained the same way that final timing analysis does; the .sdc that works for TimeQuest works for the Fitter too. My point with my example where the LUT name is used in the Fitter report and the register name is used in the TimeQuest reports is that the Fitter report will let you find out about that LUT-driven clock that is generally a discouraged design practice for FPGAs. Even after you constrain the clock at the point of the register in the clock path, you would never know from just the TimeQuest reports that there was a LUT in the clock path after that register unless you happened to use report_timing to look at the clock detail in a path using that clock.

[Altera_Forum]

--- Quote Start ---  I discovered this soon after I placed the last post. In addition to Remove Duplicate Registers - OFF, I also set Remove Redundant Logic Cells - OFF. After I did this, and then reran the compilation, the synthesis tool reported it was elaborating the instance that was being removed. So this command definitely worked.  --- Quote End ---    Just to be clear, Quartus II does not elaborate (generate an initial netlist from the HDL) every single instance in the design. If two instances are instantiating the same entity + parameter/generic overrides and the two instances don't differ in any assignments that might affect elaboration, you'll only see one message such as, elaborating entity "foo" for hierarchy foo:inst". . Later, the compiler will replicate the netlist for the duplicate hierarchies when it starts stitching together the final netlist for the design. It doesn't duplicate extract at the level of user instances - it only identifies duplicate gates, mxes, operators, registers, etc and those algorithms run mostly on the flat netlist.

[Altera_Forum]

Is there a command/pragma/etc that can be placed in the schematic so that I wouldn't have to use the Assignment Editor? 

 I'm used to having a command called "uniquify" in Design Compiler, which will make unique instances of all entity/arch or modules that it finds in a design. Once that is done, the compiler proceeds as normal. I suppose using the Assignment Editor is basically the same thing, correct?

[Altera_Forum]

Quartus II and Design Compiler are implementing different optimization flows. You don't need a "uniquify" command in Quartus II - the compiler already creates unique netlists for each instance and optimizes them using their appropriate context in the design, e.g. some inputs tied to constants. What you don't like is the way Quartus II merges duplicate logic from unique hierarchies, which can be disabled by assignment. If you want to embed the assignment in HDL, use altera_attribute 

 (* altera_attribute = "-name REMOVE_DUPLICATE_LOGIC off" *) module m(...);  or in your entity  library altera; use altera.altera_syn_attributes.all;  entity E is   generic (...);  port (...);   attribute altera_attribute of E : entity is "-name REMOVE_DUPLICATE_LOGIC off";  end entity E;  Also, REMOVE_DUPLICATE_LOGIC preserves duplicate logic cones AND duplicate registers. REMOVE_REDUNDANT_LOGIC_CELLS only protects duplicate LCELL buffers and WYSIWYGs, i.e. it doesn't protect duplicate logic cones that don't feed an LCELL buffer.  Why are you concerned about duplicate logic extraction? Timing? If you simply want to make assignments to registers in the duplicate hierarchy, go ahead and do so. If two duplicate registers have different assignments, the synthesis engine won't merge them.