Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
15385 Discussions

Synthesized away the following RAM node help

Honored Contributor II

Hi all,


when I compile my code, I receive the warning which my RAM nodes q_a is synthesized away. (Not sure what does this mean)


I have two RAMs, m1 and m2, both 32x128 true dual port rams. What I do is the following:


1. Read 2 numbers from m1, and input q_a & q_b into a compare module and save the smaller one to m2. (Try to implement Merge Sort between 2 RAMs)

2. After all the number is compared, transfer data back to m1.


The following is the code of connecting the components (RAM1, RAM2 to compare hardware module)


... ...

MgHwM : merg_hw_module


... ...

ToM1AdrA => m1_adr_a,

ToM1AdrB => m1_adr_b,

ToM1DataA => m1_data_a,

ToM1DataB => m1_data_b,

ToM1RdenA => m1_rden_a,

ToM1RdenB => m1_rden_b,

ToM1WrenA => m1_wren_a,

ToM1WrenB => m1_wren_b,

FromM1QA => m1_q_a, ------------------------------------------------- q_a of m1 is enter via this port

FromM1QB => m1_q_b, ------------------------------------------------- q_b of m1 is enter via this port

ToM2AdrA => m2_adr_a,

ToM2AdrB => m2_adr_b,

ToM2DataA => m2_data_a,

ToM2DataB => m2_data_b,

ToM2RdenA => m2_rden_a,

ToM2RdenB => m2_rden_b,

ToM2WrenA => m2_wren_a,

ToM2WrenB => m2_wren_b,

FromM2QA => m2_q_a, ----------------------------------------------- q_a of m2 is enter via this port

FromM2QB => m2_q_b ------------------------------------------------ q_b of m2 is enter via this port



And attached is the compare code:


For some reason, the q_a for m1 (which corresponding the FromM1QA), the q_b for m2 (which corresponding to FromM2QB ) are synthesized away.


Can anyone help? 



0 Kudos
1 Reply
Honored Contributor II

I assume you have not simulated this code, otherwise you would know that ele_num is never assigned a value, and hence it remains at it's initial value, -2147483648, it then underflows (illegal in vhdl) because you multiply it by pair. 

ToM1AdrA is assign from either this massively negative value, or 0, as it also comes from wr2, which is only ever assigned to 0. 


If mhm_rd1_ubound and mhm_rd2_ubound are set to some poor value, then this would remove the option ToM1AdrA to the bad integer, and keep it held at 0. 


Things I recommened: 

1. Do not use unconstrained integers 

2. Do not use variables - use signals instead - there is NOTHING you need variables for that you cannot use signals for (and signals are much easier to debug and map better to hardware for beginners) 

3. Suimulate your code, write a testbench. 

4. Why have you got initial values on your outputs? these will only take effect if they are not assigned in your code.