System Verilog: Overridden members system verilog classes

[Altera_Forum]

class my_a; 

int member1 = 1; endclass class my_ea extends my_a; int member1 = 2; endclass Now when I do my_a a; my_ea ea; ea =new(); a=ea; ================================================== ========== ea = new(); has given handle to object of type my_ea to class variable EA. a=ea; This pass the same handle (pointer value which points to object of my_ea) to A. so , A.member1 should refer to value 2. But it refer to value 1. why?

[Altera_Forum]

This is because you declared A as class my_a, therefore you only have visibility of variables/functions declared in the my_a class. If you want to see member1 from the my_ea class you will need to cast A to the my_ea class. 

 This is important because you can have many sub-classes of my_a, with an array of variables all of different classes. The compiler can only see the class of the variable type, it doesnt know what class it is from the handle.  This can get a little confusing with virtual/non virtual functions. non-virtual functions will always call the function from the class type of the variable. virtual functions will always call the function from the class declared by the handle, because they get overridden in the base classes.