[SystemVerilog] Passing "inout" thru verbatim

Altera_Forum · ‎03-25-2014

Hi all,

I have an Altera DE2-115 board and am working on interfacing with the asynchronous static RAM chip. I have gotten a simple test harness working, but only if it is the top-level entity. (See "asram_demo" below.)

However, obviously, I do not want to use this as a top level entity, as it's intended to evolve into a full SRAM controller. In fact, I have no idea how I could have multiple top-level entities anyway.

So, my next step was to have another actual top-level entity (called "DE2ASRAM") instantitate the "asram_demo" and pass the wires through verbatim before adding additional logic.

However, this leads to the following error:

Error (10663): Verilog HDL Port Connection error at DE2ASRAM.sv(17): output or inout port "SRAM_DQ" must be connected to a structural net expression

This does not in the slightest help me understand the problem or what to do about it. All I want to do is directly connect the incoming SRAM_DQ to the instantiated module's SRAM_DQ. But, it doesn't work.

I welcome any pointers or help here. How can I accomplish this?

Thanks!


module asram_demo(
                       // DE2 keys, switches
                       input  logic  SW,
                       input  logic   KEY,
                       output logic  LEDR,
                       output logic   LEDG,
                       // ASRAM Chip Lines
                       output logic  SRAM_ADDR,  // Address inputs
                       inout  logic  SRAM_DQ, // Data inputs/outputs
                       output logic SRAM_CE_N,      // Chip enable
                       output logic SRAM_OE_N,      // Output enable
                       output logic SRAM_WE_N,      // Write enable
                       output logic SRAM_LB_N,      // Lower byte control (I/O 0-7)
                       output logic SRAM_UB_N       // Upper byte control (I/O 8-15)
                  );
  logic enable_io_output; // Send data to SRAM?
  logic  io_output;
  logic enable_ledr_output; // Display data on LEDR?
  logic  ledr_output;
  // Remember: KEYs are HIGH (1) when NOT pressed,
  // so it really should be called KEY_n
                  
  // We always leave the ASRAM chip enabled
  assign SRAM_CE_N = 1'b0;
  
  // We always do word-at-a-time access
  assign SRAM_LB_N = 1'b0;
  assign SRAM_UB_N = 1'b0;
  // Switches 0-9  : Data input        (10)
  // Switches 12-17: Address selection (6)
  // Key 0: Output enable
  // Key 1: Write enable
  
  // Keys
  assign SRAM_OE_N = KEY;
  assign SRAM_WE_N = KEY;
  
  // Address
  assign SRAM_ADDR = {14'b0, SW};
  // Data - this is the hard part.
  // We load the LEDR from the SRAM_DQ when we're reading,
  // but we load the SRAM_DQ from the switches when we're writing.
  // We don't output to LEDR unless we're reading.
  assign SRAM_DQ = enable_io_output ? io_output : 16'bZ;
  assign LEDR = enable_ledr_output ? ledr_output : 18'bZ;
  
  always_comb begin
    io_output = 16'b0;       // Default output value (to avoid a latch)
    enable_io_output = 1'b0; // Don't enable output if unnecessary
    ledr_output = 18'bZ;     // Wonder if this will work...
    enable_ledr_output = 1'b0;
    if (~KEY) begin // We're writing, so use I/O lines as output
      io_output = {6'b0, SW};
      enable_io_output = 1'b1;
    end else if (~KEY) begin // We're reading and NOT writing, so use I/O lines as input
      ledr_output = {2'b0, SRAM_DQ};
      enable_ledr_output = 1'b1;
    end
  end // always_comb
endmodule


module DE2ASRAM(
                       // DE2 keys, switches
                       input  logic  SW,
                       input  logic   KEY,
                       output logic  LEDR,
                       output logic   LEDG,
                       // DE2 SRAM
                       output logic  SRAM_ADDR,
                       inout  logic  SRAM_DQ,
                       output logic        SRAM_CE_N,
                       output logic        SRAM_OE_N,
                       output logic        SRAM_WE_N,
                       output logic        SRAM_LB_N,
                       output logic        SRAM_UB_N
               );
  // The error is in the following line, regardless of
  // the way I enter the parameters.
  asram_demo demo(.*);
               
endmodule

Altera_Forum · ‎03-25-2014

I believe the compiler is incorrectly classifying inout logic [15:0] SRAM_DQ, as a variable, not a net declaration. Try inout wire logic [15:0] SRAM_DQ, or inout [15:0] SRAM_DQ, . Verilog and SystemVerilog are both rife with implicit declaration madness.

Altera_Forum · ‎03-25-2014

Dave!!! You solved in 36 minutes (probably really more like 30 seconds) what I have been banging my head against for two days (probably 6-8 hours of real time).

Thank you so much.

For the record: both of your suggestions work in the top level module declaration:


inout  SRAM_DQ,
inout wire logic  SRAM_DQ,

Needless to say I will have copious comments in my code describing this oddity.

Cheers!