Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)

Timequest Timescale

Altera_Forum
Honored Contributor II
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Are timequest timing constraints always in nanseconds? I have trawled through the documents, the help system, the forum and via Gxxgle, finding nothing. If I put "5ns" in an SDC is the ns ignored? 

 

Cheers,
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Are timequest timing constraints always in nanseconds? I have trawled through the documents, the help system, the forum and via Gxxgle, finding nothing. If I put "5ns" in an SDC is the ns ignored? 

 

Cheers, 

--- Quote End ---  

 

 

excerpt from altera doc: 

 

"Enter time values in default time units of nanoseconds (ns) with up to three decimal 

places. Note that the TimeQuest analyzer does not display the default time unit when 

it displays time values. 

You can specify a different default time unit with the set_time_format -unit <default 

time unit> command, or specify another unit when you enter a time value, for 

example, 300ps." 

 

You can also define frequency of clocks as -period "<val> MHz" but this is not standard sdc but unique to TQ
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Altera_Forum
Honored Contributor II
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Thanks, Kaz, that's exactly what I wanted to know. Where did you find it? 

Regards, 

Simon
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Thanks, Kaz, that's exactly what I wanted to know. Where did you find it? 

Regards, 

Simon 

--- Quote End ---  

 

 

not easy to find. 

 

qts_qii53019.pdf 

topic: switching to quartus timequest timing analyser 

timing units, page 8-6
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Altera_Forum
Honored Contributor II
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Ah, now I know what to look for, it is also in the SDC and TimeQuest API Reference Manual, although not in the November 2008 version which I printed out long ago. 

 

As an observation, there are a huge number of documents explaining SDC constraints, for an end result of a few sentances of commands at least for the average FPGA. I can't help feeling that the concept is flawed if it is so difficult to use. 

 

Regards, 

Simon
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