SystemVerilog type parameters not supported in Quartus Lite?

[zener]

I found that SystemVerilog modules which I can simulate in Questa, Synopsys VCS, Vivado xsim and Verilator, synthesize in Vivado (free version) and Quartus Pro does not synthesize in Quartus Lite.

I assume that this might be since Quartus Lite will not let me set VERILOG_INPUT_VERSION to SYSTEMVERILOG_2012.

I'm using the same RTL repository of Verilog modules for multiple designs and multiple FPGA/ASIC targets. Some of these have type parameters which is not accepted by Quartus Lite. VERILOG_INPUT_VERSION is set to SYSTEMVERILOG_2005 which is the most recent SystemVerilog standard accepted in the Lite version.
I get the following error:
Error (10170): Verilog HDL syntax error at core.sv(18) near text: "type"; expecting an identifier ("type" is a reserved keyword ).

Again this is a type parameter and it's accepted by all the other tools mentioned when passing it the exact same file.

My Quartus Pro version is
Version 24.3.1 Build 102 01/14/2025 SC Pro Edition

My Quartus Lite version is
Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition

Both running under Linux.

Some questions related to the type parameter limitation:

1) Is this limitation related to the Quartus version or is related to Pro vs Lite?
2) If the latter, is this limitation present in Quartus Lite only, or is it present in Quartus Standard as well?
3) Are the valid values for VERILOG_INPUT_VERSION available when running quartus_sh in tcl batch mode?
E.g. if I set it to SYSTEMVERILOG_2012 I will get an error. It would be better is I could check it against a set of valid values e.g. if it should be available in the Lite version eventually and also when SYSTEMVERILOG_2017 and SYSTEMVERILOG_2023 will be supported in Quartus Pro
4) Is the removal of type parameters in Lite intentional?
5) There is no mention of SystemVerilog language support differences in:
https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2023-11/quartus-prime-comparison-infographic.pdf
Shouldn't this limitation be documented in here?

[ShengN_Intel]

Hi,

Sent you an email.

[FvM]

Hi,
up to now, most detailed spec of HDL support for Quartus was available in Quartus help file. While Quartus pro has updated help for V 24.3, Quartus Std/Lite seems to be stuck at help for V 18.1 which is still delivered with most recent version. I conclude that no functional changes or enhancements took place since then. Is it true?

Generally, I remember it has been stated that Quartus Std./Lite has limited language support compared to Pro. Would be interesting to hear about plans for improvement.
Regards
Frank

[zener]

This is somewhat problematic as I can't use utility libraries like pulp-platform with Quartus Std/Lite:

https://github.com/pulp-platform/common_cells/blob/master/src/shift_reg.sv

It might be possible to use various pre-processors to compile SystemVerilog-2012 into plain Verilog or older SystemVerilog versions, but this requires modification to the current flow.

Even professional users with a Pro license might want to re-use their verified RTL libraries when targeting low end devices.

[ShengN_Intel]

Hi,

Have you see the personal email sent to you previously?

Thanks,

Regards,

Sheng