Hi all,
I have a project with som source synchronous interfaces and some other interface with same external clock source and I've to set the output delay constraints.
I had all the documentations by Altera and Ryan and the things are quite clear (I hope) but I've just one question:
A. The virtual clock have the same frequency of my PLL output.
b. There is the possibility that in my project the PLL parameters change in future and consequently the clock will have different frequencies.
the problem is that any change in the PLL force me to change all the time the frequency of the virtual clock in the sdc, despite they are always the same.
Is it possible in the sdc to "extract" the period of a clock (the PLL output ex |U_altpll0|altpll_component|auto_generated|pll1|clk[0]) and use as variable for the virtual clock ?
I thought also to use a generated clock from the PLL output (-add option?) but in this case i cannot add the external delays in conjunction with clock uncertainty or in any case I'm not user is right even in the source synchronous case (still better the virtual clock with create clock?)
thanks in advance for any suggestion
