TTTL finder / output and input

[Altera_Forum]

Hello,I want to create a circuit which has two inputs a clock and an enable and three outputs. What I want this circuit to do is that it has a variable (cont) that goes from "00" to "11" and two of the outputs (sal_1 and sal_2) take the values of cont(0) and cont(1) and go to the inputs of a ttl ic (AND , OR, XOR) and then the output of the ttl ic goes back to the circuit and is saved (results) after that, the vector that is created from the differents results of the ttl ic ouputs is compared with vectors already predefined and find the one that matches it and returns the value.I have a hard time with the output and then input times, it seems that there is a special way to do this.Here is my code:library IEEE;use IEEE.std_logic_1164.all;use IEEE.numeric_std.all;use IEEE.std_logic_unsigned.all;use IEEE.std_logic_arith.all;entity ttl_finder is port( clk, ena, sal_ttl : in std_logic; sal_1, sal_2 : out std_logic; sal_f : out std_logic_vector(3 downto 0));end entity;architecture ttl_tester of ttl_finder issignal cont : std_logic_vector(1 downto 0) := "00";signal results : std_logic_vector(3 downto 0) := "0000";beginprocess(clk, ena)variable c : std_logic;variable d : std_logic;variable e : std_logic;beginif ena = '1' then if cont < "11" then sal_1 <= cont(0); sal_2 <= cont(1); if rising_edge(clk) then results(conv_integer(cont)) <= sal_ttl; end if; cont <= cont + 1; else sal_1 <= cont(0); sal_2 <= cont(1); if rising_edge(clk) then results(conv_integer(cont)) <= sal_ttl; end if; cont <= "00"; end if;end if;end process;sal_f <= results;end ttl_tester;

[Altera_Forum]

You should probably register the whole process using the input clock. I'm not sure what is going on external to this process, like what is driving the enable and clock signals, but if you clocked your process with clk the code for your process would look like this: 

 begin if rising_edge(clk) then if ena = '1' then sal_1 <= cont(0); sal_2 <= cont(1); results(conv_integer(cont)) <= sal_ttl; cont <= cont + 1; end if; end if; end process;  I'm not sure this is really what you want but it is much cleaner code. The reason you don't need a special if statement to handle the case when cont="11" is that when you add cont <= cont +1 you will get "00" as the output which is what you were setting the value to anyway. So, actually, both your if and else statements were performing identical processes. (Also, you should only have one if rising_edge(clk) statement in a process, also, you should probably add a reset state).  By registering the code like this, however, the result vector is always going to trail the value of cont by one clock cycle so you may want to adjust the index into results accordingly. I suggest you draw out the circuit you want to implement on a piece of paper and go through what happens at each point in the processes at each clock cycle.  Hope this helps!

[Altera_Forum]

--- Quote Start ---   It does help a lot, sorry I'm still a newbie in VHDL. The whole point of my proyect is that I want to connect to a TTL chip like an AND (7408) to a Spartan 3. Two inputs will come from the Spartan 3 to the TTL and of course the TTL chip would be connected to a voltage so it can work. Then take the output of the TTL and make it go back to the Spartan so it can be saved in a vector. I want to do this four times for cont = 00, 01, 10 and 11, so after all these entries, the final vector (results) would be a vector that I can read and tell which TTL is the one I'm testing. But I have trouble with the clocks and test bench.  Your code works really well but I'm trying to test it and it doesn't work. Hope you can help me with this. Thanks.   --- Quote End ---     LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY ttl_finder_tst IS END ttl_finder_tst; ARCHITECTURE behavior OF ttl_finder_tst IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT ttl_finder PORT( clk : IN std_logic; ena : IN std_logic; sal_ttl : IN std_logic; sal_1 : OUT std_logic; sal_2 : OUT std_logic; sal_f : OUT std_logic_vector(3 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal ena : std_logic := '0'; signal sal_ttl : std_logic := '0'; --Outputs signal sal_1 : std_logic; signal sal_2 : std_logic; signal sal_f : std_logic_vector(3 downto 0); -- Clock period definitions constant clk_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: ttl_finder PORT MAP ( clk => clk, ena => ena, sal_ttl => sal_ttl, sal_1 => sal_1, sal_2 => sal_2, sal_f => sal_f ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100 ns. wait for 20 ns; ena <= '1'; sal_ttl <= sal_1 and sal_2; -- Here im trying to recreate the TTL wait; end process; END;

[Altera_Forum]

--- Quote Start ---   Your code works really well but I'm trying to test it and it doesn't work.   --- Quote End ---    Can you explain this a little better? In what way does it "work really well" and in what way does it not work? Are you getting an incorrect output? No output? Please explain.

[Altera_Forum]

Not sure if this is related to your problem but... you may need to adjust the code as shown below to account for the fact that on each clock cycle you are actually processing the result out of the TTL due to the the previous state of "cont". This way it will index into the "results" vector correctly. 

  signal prev_cont : std_logic_vector(1 downto 0) := "00"; -- Include this line in your architecture begin if rising_edge(clk) then if ena = '1' then sal_1 <= cont(0); sal_2 <= cont(1); results(conv_integer(prev_cont)) <= sal_ttl; -- change this to look at the previous value prev_cont <= cont; -- set previous value to current value of cont cont <= cont + 1; end if; end if; end process;