Problem simulating design with LPM_FF with ModelSim/Altera, works OK with QSim

[Altera_Forum]

Hello, 

 I have a problem simulating LPM_FF megafunction, I have created a project with a bdf file, containing just LPM_FF, placed pins on all inputs/outputs, set LPM_WIDTH to 4, compiled the project with no errors, generated VHDL code from bdf file, replaced bdf with the created vhd file in the same project, compiled it again with no errors, run "Analysis and Elaboration" with no errors, than run "RTL simulation" - started ModelSim / Altera, to simulate design, I apply clock and set "enable" on logic '1' rest of the signals on '0', Din[3..0] = 1010 and regardless how I set any remaining signals, the Output Q[3..0] will be shown red as "UUUU".  I have tried to simulate same design using QSim, using same simulation conditions, when I have applied logic '1' to asynchronous load pin, Din was loaded on Output - and Q[3..0] has become as expected '1010'.  Setup: QuartusII 11.1 32bit Web Edition, ModelSim Altera Starter Edition 10.1e  Any ideas about what am I doing wrong in simulating design with ModelSim Altera or using LPM_FF will be greatly appreciated !  Regards

[Altera_Forum]

Hello 

 I have tried to simulate this design with ModelSim Altera V6.5 and 10.0e both show same results - I have attached a picture with the schematic and simulation results. Am I doing something wrong ? This schematic is too simple to give me so much grief ... :)  Regards

[Altera_Forum]

Are you input and output pins actually connected to the block? move them away from the LPM_FF in the schematic and see if there are wires joining the pins - its happened to me in the past (another reason schematics are best avoided).

[Altera_Forum]

Yes, all pins are connected to the module.

[Altera_Forum]

Can you post the VHDL generated from the module and the testbench?

[Altera_Forum]

Hello, 

  I have attached whole project folder made with Quartus 11.1sp2, including simulation folder.  Regards.