Test stimulus for FPGA validation

[HTolentino]

Hello,

I am trying to do test validation for my project and was wondering how to implement a test stimulus.

I want to make clear I am not wanting to functionally verify such as using a testbench for ModelSim - as I have already done this. 

What I want to see  is if the signals actually behave the same way after being implemented in the FPGA

My intuition is using SignalTap as it allows us to track signals on an FPGA.

However, my only experience with it is seeing push buttons and triggers.

Even the ISSP, if I recall correctly, requires manual tuning of the signals bit by bit using force commands - I dont think this is really efficient for large scale.

My code is a finite state machine that relies on certain inputs and is synchronous to a clock.

Is providing a test stimulus something simple I am missing or does require some script or something?

PS - I notice that there is a system memory content editor but I dont know if this is what I really want.

Thank you

[sstrell · Accepted solution]

The tools you mention are all for on-chip debugging with the design running in hardware.  This seems to be what you want to do.

If you are saying you want to toggle internal signals while the design is running, then ISSP is what you want.  You can use it along with Signal Tap to see more high-speed signaling as you toggle signals (ISSP probe data is only available as fast as the JTAG connection).  You can set up a Signal Tap trigger based on the ISSP source toggling or anything else that should be happening while the design is running.

In-System Memory Content Editor is for viewing and editing the contents of on-chip RAM blocks during runtime.  That doesn't seem like what you want.

[HTolentino]

Hello sstrell and ShengN_Intel,

Thank you for the reply. 

My problem with ISSP is that if I want to change the sources, I have to do it manually change it bit by bit.

I have 16 bit input that changes every clock cycle which presents a challenging task.

I looked at the link ShenN provided and I think I am right to assume that the GUI only allows a direct push button approach.

What I am really looking for is a way for Quartus to take in a test stimuli in some sort of file format like a text file.

I brought up the In content memory editor because I saw a tutorial about it.  https://www.youtube.com/watch?v=YI34AoA74_c

At first I brushed it off, but upon looking at it more yesterday I think it actually makes sense.

Essentially, the test stimuli can be stored in a ROM, then an up counter (connected to the address of the ROM) calls the data/stimuli stored in the ROM.

It kind of reminds of a processor reading an instruction set.

So this way, I think we can just write in the MIF file and test it.

Please let me know if I misunderstood something.

Thank you.

-htolentino

[ShengN_Intel]

Hi,

This link https://www.intel.com/content/www/us/en/support/programmable/support-resources/design-software/debugging.html provides further information on on-chip debugging probably can help you out.

Thanks,

Best Regards,

Sheng

[sstrell]

Sure, you could use ISMCE if you want to add the memory and the ability to read it.

In ISSP, you can group sources into a vector and set them all to the values you want in one shot if that is what you are looking for.  If it's more complicated than that then you might want to even think about adding a Nios processor and writing software for testing the design.

[ShengN_Intel]

Hi htolentino,

Do you have any further update or concern?

Thanks,

Sheng

[HTolentino]

Thank you for the assistance ShengN_Intel and sstrell

[SyafieqS]

I let this to close pending