The basic theory about static timing analysis

[Altera_Forum]

I just have a question about STA, does STA only working for synchronous circuit？ 

 Thanks very much.

[Altera_Forum]

Nobody help me?

[Altera_Forum]

Are you asking about "the basic theory of STA" or the abilities of it's implementation in Quartus and TimeQuest?

[Altera_Forum]

--- Quote Start ---  Are you asking about "the basic theory of STA" or the abilities of it's implementation in Quartus and TimeQuest?  --- Quote End ---    Let us ask like this way, since in FPGA, we always do Synchronous Design, so I think STA in TimeQuest is always used to analyse synchronous design. But in theory, does that mean STA only be used for synchronous design? Can I use STA to analyse asynchronous design?   Thanks very much.

[Altera_Forum]

You can analyse an asynchronous design only in part. Delay of combinational logic yes, also up to a latch or asynchronous register input, but not across latches and asynchronously operated registers. The problem is discussed in the TimeQuest user manual written by Rysc.

[Altera_Forum]

--- Quote Start ---  You can analyse an asynchronous design only in part. Delay of combinational logic yes, also up to a latch or asynchronous register input, but not across latches and asynchronously operated registers. The problem is discussed in the TimeQuest user manual written by Rysc.  --- Quote End ---    Thanks very much, FvM. I should read the manual again.

[Altera_Forum]

Excluding very tiny cpld designs and board glue logic, no one is practically supposed to use asynchronous designs in FPGAs and ASICs. The timing tools are meant for synchronous design. The verdict of pass/fail is about speed and is centred on the notion of timing window of clocked registers. The additional delay data given is just informative side issue.  

 Asynchronous dsign is however a speciality on its own and if successful can be very fast as it is limited only by race condiotions due to variable delays and not by any register timing window. "Achronix" was trying to make special fpgas for very fast asynchronous design that will be programmed as RTL by designer but the tool will convert RTL to asynchronous. I don't know if the idea ever surfaced up.

[Altera_Forum]

--- Quote Start ---  Excluding very tiny cpld designs and board glue logic, no one is practically supposed to use asynchronous designs in FPGAs and ASICs. The timing tools are meant for synchronous design. The verdict of pass/fail is about speed and is centred on the notion of timing window of clocked registers. The additional delay data given is just informative side issue.   Asynchronous dsign is however a speciality on its own and if successful can be very fast as it is limited only by race condiotions due to variable delays and not by any register timing window. "Achronix" was trying to make special fpgas for very fast asynchronous design that will be programmed as RTL by designer but the tool will convert RTL to asynchronous. I don't know if the idea ever surfaced up.  --- Quote End ---    Thanks very much, kaz. The information is very useful.