The clock skew does not affect default setup and hold relation, right?

[Altera_Forum]

In STA using TimeQuest, the default setup relation is the closest edge pairs where Launch Edge < Latch Edge. In a simple case, the launch and latch clocks are the same one, but latch clock has a positive clock skew (e.g. 0.001). Then actually the closest edge of latch edge is just 0.001 later than launch edge. 

 But in TimeQuest, as attachment, the default setup relation has not been affected by the clock skew. So does this mean when TimeQuest calculate the default setup and hold relations, it does not consider the clock skew?  Thanks very much.

[Altera_Forum]

The setup and hold relationships are done independent of delays, and instead are based on how the clocks are described. In essence, you can determine them based on the .sdc, independent of the FPGA it's put into, how it's placed and routed, etc. 

Taking your example of 0.001ns delay difference(skew), then you would fix that with a multicycle to push the setup relationship to the next edge. If you then did another place-and-route, and the skew went to -0.001ns, then your multicycle would be wrong, i.e. you would never be able to have the correct constraints due to slight variations in the place-and-route. By having the relationships independent of the place-and-route, you avoid this.

[Altera_Forum]

--- Quote Start ---  The setup and hold relationships are done independent of delays, and instead are based on how the clocks are described. In essence, you can determine them based on the .sdc, independent of the FPGA it's put into, how it's placed and routed, etc. Taking your example of 0.001ns delay difference(skew), then you would fix that with a multicycle to push the setup relationship to the next edge. If you then did another place-and-route, and the skew went to -0.001ns, then your multicycle would be wrong, i.e. you would never be able to have the correct constraints due to slight variations in the place-and-route. By having the relationships independent of the place-and-route, you avoid this.  --- Quote End ---    Thanks very much, Rysc. Generally speaking, when we set the setup and hold relationships, I don't need to care clock skew.

[Altera_Forum]

When Rysc says "delays", he means skew, which is how you interpreted it. However, be careful because other delays, e.g. PLL offsets DO affect the setup and hold relationships. A clock crossing between two clocks of the same frequency; one with 0 ps offset and one with 100 ps offset would be treated very differently than a 100 ps clock skew between two identical clocks (due to for example different routing delays on the clocks) with respect to setup and hold relationships.

[Altera_Forum]

--- Quote Start ---  When Rysc says "delays", he means skew, which is how you interpreted it. However, be careful because other delays, e.g. PLL offsets DO affect the setup and hold relationships. A clock crossing between two clocks of the same frequency; one with 0 ps offset and one with 100 ps offset would be treated very differently than a 100 ps clock skew between two identical clocks (due to for example different routing delays on the clocks) with respect to setup and hold relationships.  --- Quote End ---    Thanks very much. Yes, I think that is Rysc mentioned " are based on how the clocks are described". I think I may express as " are based on how the clocks we configure them". For example, you mentioned PLL offsets DO, that is what we configure the PLL to make an offset in the clock signal, instead of a delay caused by routing.