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Hello Folks:
I'm a newbie on VHDL as well as Quartus II. In the practice, I trying to build a module which controls LED blinking frequency by generic input from upper entity. However, it looks like the generic value can not actually be passed into the target instance. When I inspect the command log there's a warning message show: https://alteraforum.com/forum/attachment.php?attachmentid=13428&stc=1 But I'm pretty sure the entity has generic part, which confused my for almost a week. And later I go to check *.vho file that generated by Quartus II after compilation, the generic part is missing. https://alteraforum.com/forum/attachment.php?attachmentid=13429&stc=1 So far I have no any idea to handle this problem, is there experienced coder can help me? Deeply appreciated. The source code and testbench of my project are: led_blink
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--Entity declaration
entity led_blink is
generic
(
i_ClkDiv : integer :=10
);
port
(
i_Clk : in std_logic; -- reference clock for LED
i_Enable : in std_logic; -- 1= enable LED
i_nRST : in std_logic; -- reset signal, active low
o_LedDrive : out std_logic -- signal line to control LED
);
end led_blink;
--Architecture
architecture arc_led of led_blink is
--These signals will be counters
signal loop_cnt : natural;
-- These signals will toggle at the frequencies needed
signal led_signal : std_logic := '0';
begin
MainProcess: process(i_Clk) is
begin
if rising_edge(i_Clk) then
if loop_cnt = i_ClkDiv-1 then -- -1, since counter starts at 0
led_signal <= not led_signal;
loop_cnt <= 0;
else
loop_cnt <= loop_cnt + 1;
end if;
end if;
end process MainProcess;
-- Only allow o_LedDrive to drive when i_Enable is high (and gate).
o_LedDrive <= led_signal and i_Enable;
end arc_led;
Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_led_blink is
end tb_led_blink;
architecture behave of tb_led_blink is
-- 48 MHz = 20.833 nanoseconds period
constant c_CLOCK_PERIOD : time := 100 ns;
signal r_CLOCK : std_logic := '0'; -- reference clock for LED
signal r_ENABLE : std_logic := '1'; -- 1= enable LED
signal r_NRST : std_logic := '1'; -- reset signal
signal r_ClkDiv : integer := 2;
signal w_LED_DRIVE : std_logic;
-- Component declaration for the Unit Under Test (UUT)
component led_blink is
generic
(
i_ClkDiv : integer :=10
);
port
(
i_Clk : in std_logic;
i_Enable : in std_logic;
i_nRST : in std_logic;
o_LedDrive : out std_logic
);
end component led_blink;
begin
-- Instantiate the Unit Under Test (UUT)
UUT : led_blink
generic map
(
i_ClkDiv =>5
)
port map
(
i_Clk => r_CLOCK,
i_Enable => r_ENABLE,
i_nRST => r_NRST,
o_LedDrive => w_LED_DRIVE
);
--Process to generate clock
p_CLK_GEN : process is
begin
wait for c_CLOCK_PERIOD/2;
r_CLOCK <= not r_CLOCK;
end process p_CLK_GEN;
end behave;
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vho not containing generic is no surprise to me. try use vhd of your entity. I never used vho for simulation
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