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OpenCL for FPGA sounds very exciting to me. Is it correct to view the idea of programming the targeted FPGA using OpenCL which translates to some RTL is sort of like defining the hardware architecture with software? That is.. it's actually the software that defines the hardware architecture? So a software engineer/programmer just writes the code and off goes the hardware (keeping in mind a new set of paradigms for concurrency and parallel programming..)..
I guess I just wanted to be clear from a high level perspective what kind of force OpenCL is driving on FPGAs. Thanks!Link Copied
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Short answer is yep :) So a software developer writes the kernel just like they would for other vendors and the compiler generates a hardware accelerator that implements the kernel. In OpenCL speak this compilation is referred to as offline compilation because you are compiling a binary (the hardware image) which your host application will target later. Once the hardware is compiled the accelerator is accessed by the host using the same APIs that you use for any other OpenCL vendor.
So the key difference in the technology is that the compute unit archeticture is not fixed in the FPGA so your kernel is implemented as a custom processing block whereas with ASIC vendors your kernel is compiled into microcode that is then run on a fixed archeticture.- Mark as New
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Cool. thanks for clearing that up! Sounds pretty powerful. Go Habs (for the sweep!)
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You are welcome. And an overdue Go Habs over the big bad Bruins :)
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