Three Port Register File

[Altera_Forum]

Use VHDL to design a model of a three port register file. The register fileis composed of eight 8-bit registers. The register file has two 8-bit outputs(ports A and B ) and a single 8-bit input (port C). Each port has an associated3-bit address input for selecting one of 8 registers for output (A and B ports)or input (C port). Port C has an associated Clk signal for transferring theinput on port C to the addressed register on the falling edge of the Clksignal. Your model should beparameterized to allow the number and bit-width of the register file to bescaled using generic parameters. 

 I'm having trouble doing this assignment. I was wondering if there was anyone that could help. I know I'm supposed to assign the values A,B,C to A_adr, B_adr, and C_adr, respectively.    library ieee; use ieee.std_logic_1164.all; entity regfile is generic ( dw : natural := 8; size : natural := 8; adrw : natural := 3); port ( A : out std_logic_vector(dw-1 downto 0); B : out std_logic_vector(dw-1 downto 0); C : in std_logic_vector(dw-1 downto 0); A_adr : in std_logic_vector(adrw downto 0); B_adr : in std_logic_vector(adrw downto 0); C_adr : in std_logic_vector(adrw downto 0); W_Clk : in std_logic); end entity regfile;

[Altera_Forum]

--- Quote Start ---  Use VHDL to design a model of a three port register file. The register fileis composed of eight 8-bit registers. The register file has two 8-bit outputs(ports A and B ) and a single 8-bit input (port C). Each port has an associated3-bit address input for selecting one of 8 registers for output (A and B ports)or input (C port). Port C has an associated Clk signal for transferring theinput on port C to the addressed register on the falling edge of the Clksignal. Your model should beparameterized to allow the number and bit-width of the register file to bescaled using generic parameters.  I'm having trouble doing this assignment. I was wondering if there was anyone that could help. I know I'm supposed to assign the values A,B,C to A_adr, B_adr, and C_adr, respectively.    library ieee; use ieee.std_logic_1164.all; entity regfile is generic ( dw : natural := 8; size : natural := 8; adrw : natural := 3); port ( A : out std_logic_vector(dw-1 downto 0); B : out std_logic_vector(dw-1 downto 0); C : in std_logic_vector(dw-1 downto 0); A_adr : in std_logic_vector(adrw downto 0); B_adr : in std_logic_vector(adrw downto 0); C_adr : in std_logic_vector(adrw downto 0); W_Clk : in std_logic); end entity regfile;  --- Quote End ---    I don't see your assignment clear enough or purposeful though the coded interface is clear (but address must be 3 bits not your 4 bits). I have to guess that the 3 bit addressing implies pointing to one of 8 bits of A,B,C byte. In that case you are talking about bit mapping from C byte to A & B bytes according to incoming addresses. As such you can only map one bit per clock and then may be wait until all 8 bits are mapped but then it depends how addressing is expected.  So you need to tell us how addressing is expected.

[Altera_Forum]

All that I posted before is what was assigned. My professor did not say anything about how addressing is expected.

[Altera_Forum]

--- Quote Start ---  All that I posted before is what was assigned. My professor did not say anything about how addressing is expected.  --- Quote End ---    In that case I will assume it is direct single bit mapping from C to A,B. you may try a clocked process with case statement:   ... case C_adr is when 0 => A(to_integer(unsigned(A_adr))) <= C(0); B(to_integer(unsigned(B_adr))) <= C(0); when 1 => A(to_integer(unsigned(A_adr))) <= C(1); B(to_integer(unsigned(B_adr))) <= C(1); etc...   Thus only one bit is mapped per clock  you may also just write the following statement in the clocked process: A(to_integer(unsigned(A_adr))) <= C(to_integer(unsigned(C_adr))); B(to_integer(unsigned(B_adr))) <= C(to_integer(unsigned(C_adr)));  but that may upset your professor as it gets too short a job for an assignment. It is also good idea to register your input C and addresses first.