TimeQuest Clock uncertainty

[Altera_Forum]

Hello everybody 

 Is adding clock uncertainty in TimeQuest a good idea when timing analysis says that everything is OK but the Design still does not operate correctly? Can clock uncertainty lead to a more robust fitting result or a more pessimistic timing analysis?

[Altera_Forum]

--- Quote Start ---  Hello everybody  Is adding clock uncertainty in TimeQuest a good idea when timing analysis says that everything is OK but the Design still does not operate correctly? Can clock uncertainty lead to a more robust fitting result or a more pessimistic timing analysis?  --- Quote End ---     Hi Stefan,  with uncertaincy setting you define a kind of "guard band" when performing the setup and hold checks. It represents the influence of jitter or clock skew.   Is your design full constrainted ? TimeQuest reports all unconstraints input and output ports. Could be found in the folder "Diagnostic"  Kind regards  GPK

[Altera_Forum]

Thanks for the reply. I have all clocks defined but not all input and output ports. Perhaps I should do that. But will this make unseen timing problems visible? I doubt my design fails because of timing problems at the ports.

[Altera_Forum]

--- Quote Start ---  Thanks for the reply. I have all clocks defined but not all input and output ports. Perhaps I should do that. But will this make unseen timing problems visible? I doubt my design fails because of timing problems at the ports.  --- Quote End ---    Hi Stefan,  without input and output constraints you can't be sure that your system will run. You need the timing of the signals which goes into your FPGA and you also need the timing requirements of the device which is driven by the FPGA.   Can you explain a little bit more about your failing design ? Can you describe the misbehviour?  Kind regards  GPK

[Altera_Forum]

Hi pletz 

 There is a problem with my state machines now and then. Sometimes it's OK after compilation, sometimes it isn't. I can see that when I'm testing the board. TimeQuest may report zero failing paths, but the design may still not work correctly.   Let's assume we have an FPGA an ADC and a DAC (interfaces like register). The FPGA reads a value from the ADC, does some processing with it and writes the processed value to the DAC. The port constraints only affect if the data is correctly read/written to data converters. It should not affect the internal processing of the data. Am I wrong?

[Altera_Forum]

--- Quote Start ---  Hi pletz  There is a problem with my state machines now and then. Sometimes it's OK after compilation, sometimes it isn't. I can see that when I'm testing the board. TimeQuest may report zero failing paths, but the design may still not work correctly.   Let's assume we have an FPGA an ADC and a DAC (interfaces like register). The FPGA reads a value from the ADC, does some processing with it and writes the processed value to the DAC. The port constraints only affect if the data is correctly read/written to data converters. It should not affect the internal processing of the data. Am I wrong?  --- Quote End ---    Hi Stefan,  you right with your statement regarding the data. Timing violation on the ports should only generate corrupt data. Ok  What about the reset ? Are all registers connected ?   What about clock domain crossings ?  Kind regards  GPK

[Altera_Forum]

Hi petz 

 The problem is that my board has no external power on reset signal. I have one state machine that resets the others, but this one has its reset not connected. I really hope state machines start with the first state of the state list. It seems they do.  Communication between clock domains is done strictliy by DCFIFO.

[Altera_Forum]

--- Quote Start ---  Hi petz  The problem is that my board has no external power on reset signal. I have one state machine that resets the others, but this one has its reset not connected. I really hope state machines start with the first state of the state list. It seems they do.  Communication between clock domains is done strictliy by DCFIFO.  --- Quote End ---     Hi Stefan,  no reset state for the statemachines ? Can you post a simple diagramm of your design, where I can get an overview about clock and reset structure ?  Did you define false paths in TimeQuest ?  Did you use signaltap for debugging ?  Kind regards  GPK

[Altera_Forum]

Thanks for your interest so far :). 

The main reset signal is called system_reset. I hope the PDF is useful. I doubt you will find anything but here it is ;).  Unfortunately i cannot use Signaltap because the board has no jtag connection.  Below are the constraints.  # # Generated SDC file "cre_mini_fpga.out.sdc" # # Copyright (C) 1991-2009 Altera Corporation# # Your use of Altera Corporation's design tools, logic functions # # and other software and tools, and its AMPP partner logic # # functions, and any output files from any of the foregoing # # (including device programming or simulation files), and any # # associated documentation or information are expressly subject # # to the terms and conditions of the Altera Program License # # Subscription Agreement, Altera MegaCore Function License # # Agreement, or other applicable license agreement, including, # # without limitation, that your use is for the sole purpose of # # programming logic devices manufactured by Altera and sold by # # Altera or its authorized distributors. Please refer to the # # applicable agreement for further details. # # VENDOR "Altera"# # PROGRAM "Quartus II"# # VERSION "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" # # DATE "Thu Jan 07 12:24:25 2010" # ## # DEVICE "EP2C20Q240C8"# # # **************************************************************# Time Information# ************************************************************** set_time_format -unit ns -decimal_places 3 # **************************************************************# Create Clock# ************************************************************** create_clock -name {clock} -period 20.000 -waveform { 0.000 10.000 } # **************************************************************# Create Generated Clock# ************************************************************** create_generated_clock -name {clk_50M} -source -master_clock {clock} create_generated_clock -name {clk_25M} -source -divide_by 2 -master_clock {clock} }] create_generated_clock -name {clk_12M5} -source -divide_by 4 -master_clock {clock} }] create_generated_clock -name {clk_6M25} -source -divide_by 8 -master_clock {clock} }] create_generated_clock -name {clk_1M56} -source -divide_by 32 -master_clock {clock} }] create_generated_clock -name {clk_781k25} -source -divide_by 64 -master_clock {clock} }] # **************************************************************# Set Clock Latency# ************************************************************** # **************************************************************# Set Clock Uncertainty# ************************************************************** # **************************************************************# Set Input Delay# ************************************************************** set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] set_input_delay -add_delay -clock 10.000 }] # **************************************************************# Set Output Delay# ************************************************************** set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 8.000 }] set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 }] set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 set_output_delay -add_delay -clock 10.000 # **************************************************************# Set Clock Groups# ************************************************************** set_clock_groups -exclusive -group # **************************************************************# Set False Path# ************************************************************** # **************************************************************# Set Multicycle Path# ************************************************************** # **************************************************************# Set Maximum Delay# ************************************************************** # **************************************************************# Set Minimum Delay# ************************************************************** # **************************************************************# Set Input Transition# **************************************************************

[Altera_Forum]

--- Quote Start ---  Thanks for your interest so far :). The main reset signal is called system_reset. I hope the PDF is useful. I doubt you will find anything but here it is ;).  Unfortunately i cannot use Signaltap because the board has no jtag connection.   Hi Stefan,  it looks like that one of my post is mising here.   With the constrain:  set_clock_groups -exclusive -group [get_clocks {clk_50M}]    you cut all paths between the 50 MHz clock an all other clocks. Is that your intention ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---  Thanks for your interest so far :). The main reset signal is called system_reset. I hope the PDF is useful. I doubt you will find anything but here it is ;).  Unfortunately i cannot use Signaltap because the board has no jtag connection.   Hi Stefan,  it looks like that one of my post is mising here.   With the constrain:  set_clock_groups -exclusive -group [get_clocks {clk_50M}]    you cut all paths between the 50 MHz clock an all other clocks. Is that your intention ?  Kind regards  GPK  --- Quote End ---    Yes, exactly. There were a lot of timing violations between the 50MHz clock and the others, so i put the parts that run with 50MHz into a different clock domain. Data is transfered between the clock domains using dual clock FIFOs.  By the way, at the moment my design seems to work, I hope it stays like that.

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---    Yes, exactly. There were a lot of timing violations between the 50MHz clock and the others, so i put the parts that run with 50MHz into a different clock domain. Data is transfered between the clock domains using dual clock FIFOs.  By the way, at the moment my design seems to work, I hope it stays like that.  --- Quote End ---    Hi Stefan,  what did you change ????:confused:   Kind regards  GPK

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---    Hi Stefan,  what did you change ????:confused:   Kind regards  GPK  --- Quote End ---    Hi Pletz  Well that's the big problem: I don't know why my design sometimes does work and sometimes doesn't. I can make a very small change and after compilation it will not work correctly anymore. It must be some timing problems that are not detected by TimeQuest. Maybe it's just that the timing simulation can not exactly represent reality. That's why I wanted to make it more pessimistic by adding clock uncertainty.

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---    Hi Pletz  Well that's the big problem: I don't know why my design sometimes does work and sometimes doesn't. I can make a very small change and after compilation it will not work correctly anymore. It must be some timing problems that are not detected by TimeQuest. Maybe it's just that the timing simulation can not exactly represent reality. That's why I wanted to make it more pessimistic by adding clock uncertainty.  --- Quote End ---    Hi Stefan,  I'm not sure, but I still believe your problem could be reset related. Your system reset is generated by a block clock by clk6M25, but it is also used in blocks running at clk_50M. That means you have valid paths between clk_50M and clk6M25. Are they re- synchronized ?  Another reason could be the statemachines itself. Are all states defined ?   Kind regards  GPK

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---    Hi Stefan,  I'm not sure, but I still believe your problem could be reset related. Your system reset is generated by a block clock by clk6M25, but it is also used in blocks running at clk_50M. That means you have valid paths between clk_50M and clk6M25. Are they re- synchronized ?  Another reason could be the statemachines itself. Are all states defined ?   Kind regards  GPK  --- Quote End ---    Hi Pletz  No, I don't re-synchronize the reset signal. My thought was that it's pointless to synchronyze it, as the reset of the state machines and FIFOs are asynchronous anyway. Do you think this may cause problems?   I could wrap the state machines in a if-structure. Is this a good way to make a synchronous reset?   -- reset is asynchronous signal from other block state.clk = clk; if -- synchronize reset with clock of machine dff(reset, clk) then state = s0; else case state is when s0 => ... when s1 => ... when s2 => ... end case; end if; At the time I am simply using the asynchronous reset input of the machine:   state.clk = clk; state.reset = reset;

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---    Hi Pletz  No, I don't re-synchronize the reset signal. My thought was that it's pointless to synchronyze it, as the reset of the state machines and FIFOs are asynchronous anyway. Do you think this may cause problems?   I could wrap the state machines in a if-structure. Is this a good way to make a synchronous reset?   -- reset is asynchronous signal from other block state.clk = clk; if -- synchronize reset with clock of machine dff(reset, clk) then state = s0; else case state is when s0 => ... when s1 => ... when s2 => ... end case; end if; At the time I am simply using the asynchronous reset input of the machine:   state.clk = clk; state.reset = reset;   --- Quote End ---    Hi,  are you using AHDL ? I'm not very familiar with the language, but I would resync the reset with a DFF outside the statemachine. Are all statemachines as fullcase implemented ? no illegal states ?  Kind regards  GPK

[Altera_Forum]

--- Quote Start ---    --- Quote Start ---    Hi,  are you using AHDL ? I'm not very familiar with the language, but I would resync the reset with a DFF outside the statemachine. Are all statemachines as fullcase implemented ? no illegal states ?  Kind regards  GPK  --- Quote End ---   Yes, it's AHDL. I'm not sure what you mean with full case implemented. But every state has defined to which case to jump under what conditions. I'll try that with the external DFF. Thanks!

[Altera_Forum]

Other things to consider are that this may be a power / bypassing issue or perhaps a simultaneous switching noise (SSN) issue and not a timing issue. 

 We had similar issues to yours - sometimes the design would work and then with seemingly trivial design changes it would stop working. In our case it looked like the FPGA was getting "reset" (all state machines, registers, etc. went to reset state) as a result of driving certain combination's of outputs - basically SSN issues.  SSN is more likely in QFP packages and there are some forums or web info on SSN with respect to Altera parts you can search for.  If there is noise on the power lines, or marginal bypassing, it's possible this could be effecting the operation.  Changes to the design effect the routing and placement which may put susceptible signals closer to problem areas.

[Altera_Forum]

Thanks for the advice StefanLevie. Actually I'm using a Cyclone II in a 240 pin PQFP so this could be an issue. However the layout and decoupling is above average in my opinion. 

By the way I found out that some of the problems happended outside the FPGA but not all.