Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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TimeQuest Timing Analyzer Not a clock

Altera_Forum
Honored Contributor II
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I am very new to Timequest Timing Analyzer, and I am trying to constrain my FPGA project. I have 1 hardware clock 10MHz, and the rest are derived from it.  

 

I have a 1us pulse that repeats every 10ms, that is used to poll some inertial sensors. before I started playing around with the TimeQuest the pulse worked, it doesn't anymore. I have been able to constrain all of my "proper" clocks but the sample pulse that doesn't pulse anymore is listed as an unconstrained clock, even though it isn't a clock. I have tried creating a generated clock for the pulse but my timing requirements ie 10ms is out of the valid range for the tool. 

 

Is there any way that I can fix this problem?  

 

Thanks in advance, 

Michael
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Altera_Forum
Honored Contributor II
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Is the sample pulse used as clock to registers? I mean is any register edge triggered on this pulse? if so it will be treated as clock. The remedy will be to use it as clock enable with the faster clock triggering the register clock port

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