project with branches

[Altera_Forum]

Hi all 

 so far my company had one main product, and we used a mix of VHDL, VERILO and the Quartus built in schematic entry tools.  now we are going to have a few similar designs with small changes, for example different RAM , serial VS parallel LCD or in some cases just a change in pin assignment.  I'm looking for a tool that will allow me to manage everything inside one project, with something similar to# IFDEF statement in C compiler i.e. I will need to change the specific HW I'm compiling for in one place, and it will auto generate the files for me.  I am aware that I will probably will have to change all the schematic entry to VHDL or VERILOG and might even have to unify all the entries to just one of them, but that's a price I'm willing to pay...  any ideas or insights are welcomed.

[Altera_Forum]

VHDL or verilog (or maybe both together) should allow to do all these different setups with Generics and Generates (thats what they're called in VHDL, not sure what they are in verilog). With this, you can often have all your setup constants in a package that can be auto-generated from a TCL script that is invoked by Quartus when you compile a project.

[Altera_Forum]

Hi Tricky 

thanks for the reply, but I still don't understand, how can I use generics to instanciate for example serial LCD interface, for HW A and a parallel LCD interface for HW B.  I should note that I do have a working knowledge of VHDL and I have used generics for example many times in the past, but that was for the portability of small blocks. for the top entity I've always used the schematic entry, and I''d let it take care of all instantiations etc.

[Altera_Forum]

Verilog has a preprocessor, so conditional compilation can be achieved basically in the same way as for C programming. 

 I would be glad to have a similar means in VHDL, but it's not provided by the standard. Tricky is right, that it can be achieved with "Generics and Generates".  Generate allows to instantiate different versions of a component for different branches, e.g. a parallel versus a serially interfaced peripheral. Of course any part of the concurrent code, a single assignment line as well as a process block can be conditionally generated.  Inside sequential code blocks (processes or functions), you have to use if constructs with constant arguments to achieve conditional compilation.  VHDL does not provide conditional compilation for interfaces. If you want to share the same top level entity for all branches (or revisions, as they are named in the Quartus software) without generating unused pins, you can give them a virtual assignment.  By using Quartus revisions for branches, you have individual *.qsf files, including a set of assignments and a project file list for each revision. So everything up to different pin mapping, FPGA package and type, even different FPGA family can be implemented.

[Altera_Forum]

--- Quote Start ---  Hi Tricky thanks for the reply, but I still don't understand, how can I use generics to instanciate for example serial LCD interface, for HW A and a parallel LCD interface for HW B.  I should note that I do have a working knowledge of VHDL and I have used generics for example many times in the past, but that was for the portability of small blocks. for the top entity I've always used the schematic entry, and I''d let it take care of all instantiations etc.  --- Quote End ---    You can use the if...generate construct in VHDL to conditionally instantiate modules and wire them up, can't you? Except of this, in VHDL you can control the different architectures used by writing configurations.

[Altera_Forum]

Hi all 

 yes it's look like conditional generate is what I was looking for. I was unfamiliar with this option.  now I just need to convince my bosses that we should allocate enough time for this. maintenance and house keeping are always pushed back on the schedule   thanks

[Altera_Forum]

"generate" statements together with "configurations" sould allow you to do it in VHDL. 

I did it already and it worked fine.

[Altera_Forum]

With direct instantiation, you can avoid the need for configurations, as you specify the architecture when you instantiate the entity. 

 my_inst : entity my_lib.my_entity(architecture1)