Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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I'm not TQ expert, so I have some simple questions - how to constrain internal memory in fpga? Esp. dual-port RAM with different rd/wr clocks? Can single-port memory be constrained with "set_multicycle_path"? br
I have a ROM memory with internally registered data output, so it takes 2 clocks to read. Because of this output register in path I'm not sure about using 'multicycle' in this case. Is there need to constrain the memory anyway?
