Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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[TimeQuest] constraining block-RAM

Altera_Forum
Honored Contributor II
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Hello,  

I'm not TQ expert, so I have some simple questions - how to constrain internal memory in fpga? Esp. dual-port RAM with different rd/wr clocks? 

Can single-port memory be constrained with "set_multicycle_path"? 

 

br
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Altera_Forum
Honored Contributor II
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an Altera Dual Clock FIFO will already have a set_false_path between the two domains 

 

we'll need more information to see if a multicycle is the right solution for your single port RAM
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Altera_Forum
Honored Contributor II
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I have a ROM memory with internally registered data output, so it takes 2 clocks to read. Because of this output register in path I'm not sure about using 'multicycle' in this case. Is there need to constrain the memory anyway?

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Altera_Forum
Honored Contributor II
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No. Just constrain the clocks and the memory will be constrained from that.

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